URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DFPScaleb96.sv] - Diff between revs 78 and 79

Rev 78	Rev 79
Line 70...	Line 70...
`// Clock cycle 1`	`// Clock cycle 1`
`// ----------------------------------------------------------------------------`	`// ----------------------------------------------------------------------------`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) xa1a <= au.exp;`	`if (ce) xa1a <= au.exp;`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) xa1b <= au.exp + b;`	`if (ce) xa1b <= bs ? au.exp - (~b[11:0] + 2'd1) : au.exp + b;`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) bs1 <= bs;`	`if (ce) bs1 <= bs;`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) anan1 <= au.nan;`	`if (ce) anan1 <= au.nan;`
`always @(posedge clk)`	`always @(posedge clk)`
Line 98...	Line 98...
`if (ce) qnan2 <= anan1 && ma1[N4-1:N4-4]==4'h1;`	`if (ce) qnan2 <= anan1 && ma1[N4-1:N4-4]==4'h1;`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) snan2 <= anan1 && ma1[N4-1:N4-4]==4'h0;`	`if (ce) snan2 <= anan1 && ma1[N4-1:N4-4]==4'h0;`
`always @(posedge clk)`	`always @(posedge clk)`
`if (ce) begin`	`if (ce) begin`
	`infinity2 <= 1'b0;`
`if (anan1) begin`	`if (anan1) begin`
`xa2 <= xa1a;`	`xa2 <= xa1a;`
`ma2 <= ma1;`	`ma2 <= ma1;`
`end`	`end`
`// Underflow? -> limit exponent to zero`	`// Underflow? -> limit exponent to zero`