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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [DPD1000Decode.sv] - Diff between revs 55 and 56

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// ============================================================================
 
//        __
 
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
 
//    \  __ /    All rights reserved.
 
//     \/_//     robfinch@finitron.ca
 
//       ||
 
//
 
//      DPD1000Decode.sv
 
//
 
// BSD 3-Clause License
 
// Redistribution and use in source and binary forms, with or without
 
// modification, are permitted provided that the following conditions are met:
 
//
 
// 1. Redistributions of source code must retain the above copyright notice, this
 
//    list of conditions and the following disclaimer.
 
//
 
// 2. Redistributions in binary form must reproduce the above copyright notice,
 
//    this list of conditions and the following disclaimer in the documentation
 
//    and/or other materials provided with the distribution.
 
//
 
// 3. Neither the name of the copyright holder nor the names of its
 
//    contributors may be used to endorse or promote products derived from
 
//    this software without specific prior written permission.
 
//
 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
//
 
// ============================================================================
 
 
module DPD1000Decode(clk, i, o);
module DPD1000Decode(clk, i, o);
input clk;
input clk;
input [9:0] i;
input [9:0] i;
output [11:0] o;
output [11:0] o;

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