This directory is a newer version of the cores with the 'WID' parameter renamed to 'FPWID' to avoid conflicts with other modules.
This directory is a newer version of the cores with the 'WID' parameter renamed to 'FPWID' to avoid conflicts with other modules.
Also experimental and not completely implemented is the 'EXTRA_BITS' definition. EXTRA_BITS defines the number of extra precision bits to maintain for a given precision. Setting this to zero should generate the usual cores. It's sometimes desirable to maintain extra precision bits in registers which are trimmed off when a transfer to memory occurs. The EXTRA_BITS definition must be a multiple of four.
"EXTRA_BITS" was removed.
There are two versions of the cores one in verilog the other in SystemVerilog. They can be distinguished by the filename extension. Include one or the other in a project as they are using the same module names. However, the verilog versions are not likely to be updated in the future.
The SystemVerilog versions of the cores import the fp package rather than using fpConfig and fpSize. It is a little cleaner.
