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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfmul.sv] - Diff between revs 54 and 55

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Rev 54 Rev 55
Line 35... Line 35...
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
 
 
module dfmul(clk, ld, a, b, p, done);
module dfmul(clk, ld, a, b, p, done);
parameter FPWID = 108;
parameter N=33;
 
localparam FPWID = N*4;
parameter RADIX = 10;
parameter RADIX = 10;
localparam FPWID1 = FPWID;//((FPWID+2)/3)*3;    // make FPWIDth a multiple of three
localparam FPWID1 = FPWID;//((FPWID+2)/3)*3;    // make FPWIDth a multiple of three
localparam DMSB = FPWID1-1;
localparam DMSB = FPWID1-1;
input clk;
input clk;
input ld;
input ld;
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parameter PREP = 2'd0;
parameter PREP = 2'd0;
parameter ADDN = 2'd1;
parameter ADDN = 2'd1;
parameter DONE = 2'd2;
parameter DONE = 2'd2;
 
 
reg [3:0] cnt;                          // iteration count
reg [3:0] cnt;                          // iteration count
reg [5:0] dcnt;                         // digit count
reg [7:0] dcnt;                         // digit count
reg [9:0] clkcnt;
reg [9:0] clkcnt;
reg [FPWID*2-1:0] pi = 0;
reg [FPWID*2-1:0] pi = 0;
reg [FPWID-1:0] ai = 0;
reg [FPWID-1:0] ai = 0;
reg [FPWID*2-1:0] bi = 0;
reg [FPWID*2-1:0] bi = 0;
wire [FPWID*2-1:0] sum;
wire [FPWID*2-1:0] sum;
Line 129... Line 130...
        #40 ld = 1'b0;
        #40 ld = 1'b0;
end
end
 
 
always #5 clk = ~clk;
always #5 clk = ~clk;
 
 
dfmul #(108) u1 (
dfmul #(27) u1 (
        .clk(clk),
        .clk(clk),
        .ld(ld),
        .ld(ld),
        .a(a),
        .a(a),
        .b(b),
        .b(b),
        .p(p),
        .p(p),

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