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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfmul.sv] - Diff between revs 55 and 65

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Rev 55	Rev 65
Line 1...	Line 1...
`// ============================================================================`	`// ============================================================================`
`// __`	`// __`
`// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo`	`// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch@finitron.ca`	`// \/_// robfinch@finitron.ca`
`// \|\|`	`// \|\|`
`//`	`//`
`// dfmul.v`	`// dfmul.v`
Line 53...	Line 53...
`reg [1:0] st;`	`reg [1:0] st;`
`parameter PREP = 2'd0;`	`parameter PREP = 2'd0;`
`parameter ADDN = 2'd1;`	`parameter ADDN = 2'd1;`
`parameter DONE = 2'd2;`	`parameter DONE = 2'd2;`

`reg [3:0] cnt; // iteration count`
`reg [7:0] dcnt; // digit count`	`reg [7:0] dcnt; // digit count`
`reg [9:0] clkcnt;`	`reg [9:0] clkcnt;`
`reg [FPWID*2-1:0] pi = 0;`	`reg [FPWID*2-1:0] pi = 0;`
`reg [FPWID-1:0] ai = 0;`	`reg [FPWID-1:0] ai = 0;`
`reg [FPWID*2-1:0] bi = 0;`	`reg [FPWID*2-1:0] bi = 0;`
`wire [FPWID*2-1:0] sum;`	`wire [FPWID*2-1:0] sum;`
	`reg [5:0] digcnt;`

`BCDAddN #(.N((FPWID*2)/4)) u1`	`BCDAdd8NClk #(.N(FPWID/4)) ubcdm1`
`(`	`(`
`.ci(1'b0),`	`.clk(clk),`
`.a(pi),`	`.a(pi),`
`.b(bi),`	`.b(bi),`
`.o(sum),`	`.o(sum),`
	`.ci(1'b0),`
`.co()`	`.co()`
`);`	`);`

`always @(posedge clk)`	`always_ff @(posedge clk)`
`begin`	`begin`
`case(st)`	`case(st)`
`ADDN:`	`ADDN:`
`begin`	`begin`
`clkcnt <= clkcnt + 1'd1;`	`clkcnt <= clkcnt + 1'd1;`
`if (ai[FPWID-1:FPWID-4]!=4'h0) begin`	`if (ai[FPWID-1:FPWID-4]!=4'h0) begin`
	`if (digcnt=='d0) begin`
`pi <= sum;`	`pi <= sum;`
	`digcnt <= 6'd3;`
`ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;`	`ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;`
`cnt <= cnt + 1'd1;`	`end`
	`else`
	`digcnt <= digcnt - 1'd1;`
`end`	`end`
`else begin`	`else begin`
`ai <= {ai,4'h0};`	`ai <= {ai,4'h0};`
`bi <= {4'h0,bi[FPWID*2-1:4]};`	`bi <= {4'h0,bi[FPWID*2-1:4]};`
`pi <= pi;`	`pi <= pi;`
`dcnt <= dcnt - 1'd1;`	`dcnt <= dcnt - 1'd1;`
`if (dcnt==6'd0)`	`if (dcnt=='d0)`
`st <= DONE;`	`st <= DONE;`
`end`	`end`
`end`	`end`
`DONE:`	`DONE:`
`begin`	`begin`
Line 100...	Line 105...
`default:`	`default:`
`st <= ADDN;`	`st <= ADDN;`
`endcase`	`endcase`
`if (ld) begin`	`if (ld) begin`
`clkcnt <= 10'd0;`	`clkcnt <= 10'd0;`
`cnt <= 4'd0;`	`digcnt <= 6'd3;`
`dcnt <= (FPWID*2)/4;`	`dcnt <= (FPWID*2)/4;`
`pi <= {FPWID*2{1'b0}};`	`pi <= {FPWID*2{1'b0}};`
`ai <= a;`	`ai <= a;`
`bi <= {4'h0,b,{FPWID-4{1'b0}}};`	`bi <= {4'h0,b,{FPWID-4{1'b0}}};`
`st <= ADDN;`	`st <= ADDN;`

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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfmul.sv] - Diff between revs 55 and 65