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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [dfmul.sv] - Diff between revs 65 and 81

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Rev 65 Rev 81
Line 61... Line 61...
reg [FPWID-1:0] ai = 0;
reg [FPWID-1:0] ai = 0;
reg [FPWID*2-1:0] bi = 0;
reg [FPWID*2-1:0] bi = 0;
wire [FPWID*2-1:0] sum;
wire [FPWID*2-1:0] sum;
reg [5:0] digcnt;
reg [5:0] digcnt;
 
 
BCDAdd8NClk #(.N(FPWID/4)) ubcdm1
BCDAddNClk #(.N(FPWID/2)) ubcdm1
(
(
        .clk(clk),
        .clk(clk),
        .a(pi),
        .a(pi),
        .b(bi),
        .b(bi),
        .o(sum),
        .o(sum),
Line 80... Line 80...
        begin
        begin
                clkcnt <= clkcnt + 1'd1;
                clkcnt <= clkcnt + 1'd1;
                if (ai[FPWID-1:FPWID-4]!=4'h0) begin
                if (ai[FPWID-1:FPWID-4]!=4'h0) begin
                        if (digcnt=='d0) begin
                        if (digcnt=='d0) begin
                                pi <= sum;
                                pi <= sum;
                                digcnt <= 6'd3;
                                digcnt <= 6'd4;
                                ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
                                ai[FPWID-1:FPWID-4] <= ai[FPWID-1:FPWID-4] - 1'd1;
                        end
                        end
                        else
                        else
                                digcnt <= digcnt - 1'd1;
                                digcnt <= digcnt - 1'd1;
                end
                end
Line 105... Line 105...
default:
default:
        st <= ADDN;
        st <= ADDN;
endcase
endcase
if (ld) begin
if (ld) begin
        clkcnt <= 10'd0;
        clkcnt <= 10'd0;
        digcnt <= 6'd3;
        digcnt <= 6'd4;
        dcnt <= (FPWID*2)/4;
        dcnt <= (FPWID*2)/4;
        pi <= {FPWID*2{1'b0}};
        pi <= {FPWID*2{1'b0}};
        ai <= a;
        ai <= a;
        bi <= {4'h0,b,{FPWID-4{1'b0}}};
        bi <= {4'h0,b,{FPWID-4{1'b0}}};
        st <= ADDN;
        st <= ADDN;

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