| Line 5... |
Line 5... |
// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub.sv
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// fpAddsub.sv
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// - floating point adder/subtracter
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// - floating point adder/subtracter
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// - two cycle latency
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// - can issue every clock cycle
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// - can issue every clock cycle
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// BSD 3-Clause License
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// it under the terms of the GNU Lesser General Public License as published
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// Redistribution and use in source and binary forms, with or without
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// by the Free Software Foundation, either version 3 of the License, or
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// modification, are permitted provided that the following conditions are met:
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// 1. Redistributions of source code must retain the above copyright notice, this
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// along with this program. If not, see .
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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| Line 39... |
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input [MSB:0] b; // operand b
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input [MSB:0] b; // operand b
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output [EX:0] o; // output
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output [EX:0] o; // output
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// variables
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// variables
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wire so; // sign output
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wire [EMSB:0] xo; // de normalized exponent output
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reg [EMSB:0] xo1; // de normalized exponent output
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wire [FX:0] mo; // mantissa output
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reg [FX:0] mo1; // mantissa output
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assign o = {so,xo,mo};
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// operands sign,exponent,mantissa
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// operands sign,exponent,mantissa
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wire sa, sb;
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wire sa, sb;
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wire [EMSB:0] xa, xb;
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wire [EMSB:0] xa, xb;
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wire [FMSB:0] ma, mb;
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wire [FMSB:0] ma, mb;
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta, fractb;
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wire [FMSB+1:0] fracta1, fractb1;
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// which has greater magnitude ? Used for sign calc
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wire xa_gt_xb = xa > xb;
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wire xa_gt_xb1;
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wire a_gt_b = xa_gt_xb || (xa==xb && ma > mb);
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wire a_gt_b1;
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wire az, bz; // operand a,b is zero
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wire az, bz; // operand a,b is zero
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wire adn, bdn; // a,b denormalized ?
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wire adn, bdn; // a,b denormalized ?
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wire xaInf, xbInf;
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wire xaInf, xbInf;
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wire aInf, bInf, aInf1, bInf1;
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wire aInf, bInf;
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wire aNan, bNan, aNan1, bNan1;
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wire aNan, bNan;
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xad = xa|adn; // operand a exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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wire [EMSB:0] xbd = xb|bdn; // operand b exponent, compensated for denormalized numbers
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fpDecomp u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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fpDecomp u1b (.i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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// Clock #1
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// - decode the input operands
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg op1;
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fpDecompReg u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecompReg u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .exp(xb), .man(mb), .fract(fractb), .xz(bdn), .vz(bz), .xinf(xbInf), .inf(bInf), .nan(bNan) );
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always @(posedge clk)
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if (ce) op1 <= op;
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// Figure out which operation is really needed an add or
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// subtract ?
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// Clock #2
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//
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// Figure out which operation is really needed an add or subtract ?
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// If the signs are the same, use the orignal op,
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// If the signs are the same, use the orignal op,
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// otherwise flip the operation
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// otherwise flip the operation
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// a + b = add,+
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// a + b = add,+
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// a + -b = sub, so of larger
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// a + -b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + b = sub, so of larger
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// -a + -b = add,-
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// -a + -b = add,-
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// a - b = sub, so of larger
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// a - b = sub, so of larger
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// a - -b = add,+
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// a - -b = add,+
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// -a - b = add,-
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// -a - b = add,-
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// -a - -b = sub, so of larger
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// -a - -b = sub, so of larger
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wire realOp = op ^ sa ^ sb;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire realOp1;
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reg realOp2;
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wire op1;
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reg op2;
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reg [EMSB:0] xa2, xb2;
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reg [FMSB:0] ma2, mb2;
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reg az2, bz2;
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reg xa_gt_xb2;
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reg [FMSB+1:0] fracta2, fractb2;
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reg maneq, ma_gt_mb;
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reg expeq;
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always @(posedge clk)
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if (ce) realOp2 = op1 ^ sa ^ sb;
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always @(posedge clk)
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if (ce) op2 <= op1;
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always @(posedge clk)
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if (ce) xa2 <= xad;
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always @(posedge clk)
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if (ce) xb2 <= xbd;
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always @(posedge clk)
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if (ce) ma2 <= ma;
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always @(posedge clk)
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if (ce) mb2 <= mb;
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always @(posedge clk)
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if (ce) fracta2 <= fracta;
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always @(posedge clk)
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if (ce) fractb2 <= fractb;
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always @(posedge clk)
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if (ce) az2 <= az;
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always @(posedge clk)
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if (ce) bz2 <= bz;
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always @(posedge clk)
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if (ce) xa_gt_xb2 <= xad > xbd;
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always @(posedge clk)
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if (ce) maneq <= ma==mb;
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always @(posedge clk)
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if (ce) ma_gt_mb <= ma > mb;
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always @(posedge clk)
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if (ce) expeq <= xad==xbd;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #3
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//
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// Find out if the result will be zero.
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// Find out if the result will be zero.
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wire resZero = (realOp && xa==xb && ma==mb) || // subtract, same magnitude
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// Determine which fraction to denormalize
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(az & bz); // both a,b zero
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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reg [EMSB:0] xa3, xb3;
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reg resZero3;
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wire xaInf3, xbInf3;
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reg xa_gt_xb3;
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reg a_gt_b3;
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reg op3;
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wire sa3, sb3;
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wire [2:0] rm3;
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reg [FMSB+1:0] mfs3;
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always @(posedge clk)
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if (ce) resZero3 <= (realOp2 & expeq & maneq) || // subtract, same magnitude
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(az2 & bz2); // both a,b zero
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always @(posedge clk)
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if (ce) xa3 <= xa2;
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always @(posedge clk)
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if (ce) xb3 <= xb2;
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always @(posedge clk)
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if (ce) xa_gt_xb3 <= xa_gt_xb2;
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always @(posedge clk)
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if (ce) a_gt_b3 <= xa_gt_xb2 | (expeq & ma_gt_mb);
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always @(posedge clk)
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if (ce) op3 <= op2;
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always @(posedge clk)
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if (ce) mfs3 = xa_gt_xb2 ? fractb2 : fracta2;
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delay #(.WID(1), .DEP(2)) udly3a (.clk(clk), .ce(ce), .i(xaInf), .o(xaInf3));
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delay #(.WID(1), .DEP(2)) udly3b (.clk(clk), .ce(ce), .i(xbInf), .o(xbInf3));
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delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(sa), .o(sa3));
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delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(sb), .o(sb3));
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delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
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delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
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delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #4
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//
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// Compute output exponent
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// Compute output exponent
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//
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//
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// The output exponent is the larger of the two exponents,
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// The output exponent is the larger of the two exponents,
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// unless a subtract operation is in progress and the two
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// unless a subtract operation is in progress and the two
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// numbers are equal, in which case the exponent should be
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// numbers are equal, in which case the exponent should be
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// zero.
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// zero.
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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always @(xaInf,xbInf,resZero,xa,xb,xa_gt_xb)
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reg [EMSB:0] xa4, xb4;
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xo1 = (xaInf&xbInf) ? xa : resZero ? 0 : xa_gt_xb ? xa : xb;
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reg [EMSB:0] xo4;
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reg xa_gt_xb4;
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reg xa4,xb4;
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always @(posedge clk)
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if (ce) xa4 <= xa3;
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always @(posedge clk)
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if (ce) xb4 <= xb3;
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always @(posedge clk)
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if (ce) xo4 <= (xaInf3&xbInf3) ? {EMSB+1{1'b1}} : resZero3 ? 0 : xa_gt_xb3 ? xa3 : xb3;
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always @(posedge clk)
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if (ce) xa_gt_xb4 <= xa_gt_xb3;
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// Compute output sign
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// Compute output sign
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reg so1;
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reg so4;
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always @*
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always @*
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case ({resZero,sa,op,sb}) // synopsys full_case parallel_case
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case ({resZero3,sa3,op3,sb3}) // synopsys full_case parallel_case
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4'b0000: so1 <= 0; // + + + = +
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4'b0000: so4 <= 0; // + + + = +
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4'b0001: so1 <= !a_gt_b; // + + - = sign of larger
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4'b0001: so4 <= !a_gt_b3; // + + - = sign of larger
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4'b0010: so1 <= !a_gt_b; // + - + = sign of larger
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4'b0010: so4 <= !a_gt_b3; // + - + = sign of larger
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4'b0011: so1 <= 0; // + - - = +
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4'b0011: so4 <= 0; // + - - = +
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4'b0100: so1 <= a_gt_b; // - + + = sign of larger
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4'b0100: so4 <= a_gt_b3; // - + + = sign of larger
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4'b0101: so1 <= 1; // - + - = -
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4'b0101: so4 <= 1; // - + - = -
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4'b0110: so1 <= 1; // - - + = -
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4'b0110: so4 <= 1; // - - + = -
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4'b0111: so1 <= a_gt_b; // - - - = sign of larger
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4'b0111: so4 <= a_gt_b3; // - - - = sign of larger
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4'b1000: so1 <= 0; // A + B, sign = +
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4'b1000: so4 <= 0; // A + B, sign = +
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4'b1001: so1 <= rm==3; // A + -B, sign = + unless rounding down
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4'b1001: so4 <= rm3==3'd3; // A + -B, sign = + unless rounding down
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4'b1010: so1 <= rm==3; // A - B, sign = + unless rounding down
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4'b1010: so4 <= rm3==3'd3; // A - B, sign = + unless rounding down
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4'b1011: so1 <= 0; // +A - -B, sign = +
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4'b1011: so4 <= 0; // +A - -B, sign = +
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4'b1100: so1 <= rm==3; // -A + B, sign = + unless rounding down
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4'b1100: so4 <= rm3==3'd3; // -A + B, sign = + unless rounding down
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4'b1101: so1 <= 1; // -A + -B, sign = -
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4'b1101: so4 <= 1; // -A + -B, sign = -
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4'b1110: so1 <= 1; // -A - +B, sign = -
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4'b1110: so4 <= 1; // -A - +B, sign = -
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4'b1111: so1 <= rm==3; // -A - -B, sign = + unless rounding down
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4'b1111: so4 <= rm3==3'd3; // -A - -B, sign = + unless rounding down
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endcase
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endcase
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delay2 #(EMSB+1) d1(.clk(clk), .ce(ce), .i(xo1), .o(xo) );
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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delay2 #(1) d2(.clk(clk), .ce(ce), .i(so1), .o(so) );
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// Clock #5
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//
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// Compute the difference in exponents, provides shift amount
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [EMSB+1:0] xdiff5;
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always @(posedge clk)
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if (ce) xdiff5 <= xa_gt_xb4 ? xa4 - xb4 : xb4 - xa4;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #6
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//
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// Compute the difference in exponents, provides shift amount
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// Compute the difference in exponents, provides shift amount
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wire [EMSB:0] xdiff = xa_gt_xb ? xad - xbd : xbd - xad;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire [6:0] xdif = xdiff > FMSB+3 ? FMSB+3 : xdiff;
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// If the difference in the exponent is 128 or greater (assuming 128 bit fp or
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wire [6:0] xdif1;
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// less) then all of the bits will be shifted out to zero. There is no need to
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// keep track of a difference more than 128.
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// determine which fraction to denormalize
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reg [7:0] xdif6;
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wire [FMSB+1:0] mfs = xa_gt_xb ? fractb : fracta;
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wire [FMSB+1:0] mfs6;
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wire [FMSB+1:0] mfs1;
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always @(posedge clk)
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if (ce) xdif6 <= xdiff5 > FMSB+4 ? FMSB+4 : xdiff5;
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// Determine the sticky bit
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delay #(.WID(FMSB+2), .DEP(3)) udly6a (.clk(clk), .ce(ce), .i(mfs3), .o(mfs6));
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wire sticky, sticky1;
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generate
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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begin
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// Clock #7
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if (FPWID==128)
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//
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redor128 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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// Determine the sticky bit. The sticky bit is the bitwise or of all the bits
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else if (FPWID==96)
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// being shifted out the right side. The sticky bit is computed here to
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redor96 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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// reduce the number of regs required.
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else if (FPWID==84)
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
redor84 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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reg sticky6;
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else if (FPWID==80)
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wire sticky7;
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redor80 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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wire [7:0] xdif7;
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else if (FPWID==64)
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wire [FMSB+1:0] mfs7;
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redor64 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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integer n;
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else if (FPWID==32)
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always @* begin
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redor32 u1 (.a(xdif), .b({mfs,2'b0}), .o(sticky) );
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sticky6 = 1'b0;
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for (n = 0; n < FMSB+2; n = n + 1)
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if (n <= xdif6)
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sticky6 = sticky6|mfs6[n];
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end
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end
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endgenerate
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// register inputs to shifter and shift
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// register inputs to shifter and shift
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky), .o(sticky1) );
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delay1 #(1) d16(.clk(clk), .ce(ce), .i(sticky6), .o(sticky7) );
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delay1 #(7) d15(.clk(clk), .ce(ce), .i(xdif), .o(xdif1) );
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delay1 #(8) d15(.clk(clk), .ce(ce), .i(xdif6), .o(xdif7) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs), .o(mfs1) );
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delay1 #(FMSB+2) d14(.clk(clk), .ce(ce), .i(mfs6), .o(mfs7) );
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|
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wire [FMSB+3:0] md1 = ({mfs1,2'b0} >> xdif1)|sticky1;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
// Clock #8
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|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
reg [FMSB+4:0] md8;
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|
wire [FMSB+1:0] fracta8, fractb8;
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|
wire xa_gt_xb8;
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|
wire a_gt_b8;
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|
always @(posedge clk)
|
|
if (ce) md8 <= ({mfs7,3'b0} >> xdif7)|sticky7;
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|
|
// sync control signals
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// sync control signals
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delay1 #(1) d4 (.clk(clk), .ce(ce), .i(xa_gt_xb), .o(xa_gt_xb1) );
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delay #(.WID(1), .DEP(4)) udly8a (.clk(clk), .ce(ce), .i(xa_gt_xb4), .o(xa_gt_xb8));
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delay1 #(1) d17(.clk(clk), .ce(ce), .i(a_gt_b), .o(a_gt_b1) );
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delay #(.WID(1), .DEP(5)) udly8b (.clk(clk), .ce(ce), .i(a_gt_b3), .o(a_gt_b8));
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delay1 #(1) d5 (.clk(clk), .ce(ce), .i(realOp), .o(realOp1) );
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delay #(.WID(FMSB+2), .DEP(6)) udly8d (.clk(clk), .ce(ce), .i(fracta2), .o(fracta8));
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delay1 #(FMSB+2) d5a(.clk(clk), .ce(ce), .i(fracta), .o(fracta1) );
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delay #(.WID(FMSB+2), .DEP(6)) udly8e (.clk(clk), .ce(ce), .i(fractb2), .o(fractb8));
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delay1 #(FMSB+2) d6a(.clk(clk), .ce(ce), .i(fractb), .o(fractb1) );
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delay #(.WID(1), .DEP(5)) udly8j (.clk(clk), .ce(ce), .i(op3), .o(op8));
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delay1 #(1) d7 (.clk(clk), .ce(ce), .i(aInf), .o(aInf1) );
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delay1 #(1) d8 (.clk(clk), .ce(ce), .i(bInf), .o(bInf1) );
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delay1 #(1) d9 (.clk(clk), .ce(ce), .i(aNan), .o(aNan1) );
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delay1 #(1) d10(.clk(clk), .ce(ce), .i(bNan), .o(bNan1) );
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delay1 #(1) d11(.clk(clk), .ce(ce), .i(op), .o(op1) );
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #9
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// Sort operands and perform add/subtract
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// Sort operands and perform add/subtract
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// addition can generate an extra bit, subtract can't go negative
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// addition can generate an extra bit, subtract can't go negative
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wire [FMSB+3:0] oa = xa_gt_xb1 ? {fracta1,2'b0} : md1;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire [FMSB+3:0] ob = xa_gt_xb1 ? md1 : {fractb1,2'b0};
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reg [FMSB+4:0] oa9, ob9;
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wire [FMSB+3:0] oaa = a_gt_b1 ? oa : ob;
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reg a_gt_b9;
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wire [FMSB+3:0] obb = a_gt_b1 ? ob : oa;
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always @(posedge clk)
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wire [FMSB+4:0] mab = realOp1 ? oaa - obb : oaa + obb;
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if (ce) oa9 <= xa_gt_xb8 ? {fracta8,3'b0} : md8;
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wire xoinf = &xo;
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always @(posedge clk)
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if (ce) ob9 <= xa_gt_xb8 ? md8 : {fractb8,3'b0};
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always @*
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always @(posedge clk)
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casez({aInf1&bInf1,aNan1,bNan1,xoinf})
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if (ce) a_gt_b9 <= a_gt_b8;
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4'b1???: mo1 = {1'b0,op1,{FMSB-1{1'b0}},op1,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b01??: mo1 = {1'b0,fracta1[FMSB+1:0],{FMSB{1'b0}}};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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4'b001?: mo1 = {1'b0,fractb1[FMSB+1:0],{FMSB{1'b0}}};
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// Clock #10
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4'b0001: mo1 = 1'd0;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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default: mo1 = {mab,{FMSB-1{1'b0}}}; // mab has an extra lead bit and two trailing bits
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reg [FMSB+4:0] oaa10;
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reg [FMSB+4:0] obb10;
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wire realOp10;
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reg [EMSB:0] xo10;
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always @(posedge clk)
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if (ce) oaa10 <= a_gt_b9 ? oa9 : ob9;
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always @(posedge clk)
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if (ce) obb10 <= a_gt_b9 ? ob9 : oa9;
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delay #(.WID(1), .DEP(8)) udly10a (.clk(clk), .ce(ce), .i(realOp2), .o(realOp10));
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delay #(.WID(EMSB+1), .DEP(6)) udly10b (.clk(clk), .ce(ce), .i(xo4), .o(xo10));
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #11
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [FMSB+5:0] mab11;
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wire [FMSB+1:0] fracta11, fractb11;
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wire abInf11;
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wire aNan11, bNan11;
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reg xoinf11;
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wire op11;
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always @(posedge clk)
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if (ce) mab11 <= realOp10 ? oaa10 - obb10 : oaa10 + obb10;
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delay #(.WID(1), .DEP(8)) udly11a (.clk(clk), .ce(ce), .i(aInf3&bInf3), .o(abInf11));
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delay #(.WID(1), .DEP(10)) udly11c (.clk(clk), .ce(ce), .i(aNan), .o(aNan11));
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delay #(.WID(1), .DEP(10)) udly11d (.clk(clk), .ce(ce), .i(bNan), .o(bNan11));
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delay #(.WID(1), .DEP(3)) udly11e (.clk(clk), .ce(ce), .i(op8), .o(op11));
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delay #(.WID(FMSB+2), .DEP(3)) udly11f (.clk(clk), .ce(ce), .i(fracta8), .o(fracta11));
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delay #(.WID(FMSB+2), .DEP(3)) udly11g (.clk(clk), .ce(ce), .i(fractb8), .o(fractb11));
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always @(posedge clk)
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if (ce) xoinf11 <= &xo10;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #12
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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reg [FX:0] mo12; // mantissa output
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always @(posedge clk)
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if (ce)
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casez({abInf11,aNan11,bNan11,xoinf11})
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4'b1???: mo12 <= {1'b0,op11,{FMSB-1{1'b0}},op11,{FMSB{1'b0}}}; // inf +/- inf - generate QNaN on subtract, inf on add
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4'b01??: mo12 <= {1'b0,fracta11[FMSB+1:0],{FMSB{1'b0}}};
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4'b001?: mo12 <= {1'b0,fractb11[FMSB+1:0],{FMSB{1'b0}}};
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4'b0001: mo12 <= 1'd0;
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default: mo12 <= {mab11,{FMSB-2{1'b0}}}; // mab has an extra lead bit and three trailing bits
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endcase
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endcase
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delay1 #(FX+1) d3(.clk(clk), .ce(ce), .i(mo1), .o(mo) );
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// Clock #13
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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wire so; // sign output
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wire [EMSB:0] xo; // de normalized exponent output
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wire [FX:0] mo; // mantissa output
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delay #(.WID(1), .DEP(9)) udly13a (.clk(clk), .ce(ce), .i(so4), .o(so));
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delay #(.WID(EMSB+1), .DEP(3)) udly13b (.clk(clk), .ce(ce), .i(xo10), .o(xo));
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delay #(.WID(FX+1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(mo12), .o(mo) );
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assign o = {so,xo,mo};
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endmodule
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endmodule
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module fpAddsubnr(clk, ce, rm, op, a, b, o);
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module fpAddsubnr(clk, ce, rm, op, a, b, o);
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input clk; // system clock
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input clk; // system clock
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| Line 208... |
Line 376... |
output [MSB:0] o; // output
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output [MSB:0] o; // output
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wire [EX:0] o1;
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wire [EX:0] o1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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|
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fpAddsub #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
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fpAddsub u1 (clk, ce, rm, op, a, b, o1);
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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fpNormalize u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
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fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRound u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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endmodule
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endmodule
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