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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpAddsub.v] - Diff between revs 29 and 31

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//
//
//      fpAddsub.v
//      fpAddsub.v
//    - floating point adder/subtracter
//    - floating point adder/subtracter
//    - ten cycle latency
//    - ten cycle latency
//    - can issue every clock cycle
//    - can issue every clock cycle
//    - parameterized FPWIDth
//    - parameterized width
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
Line 144... Line 144...
reg [EMSB:0] xdiff3;
reg [EMSB:0] xdiff3;
// which has greater magnitude ? Used for sign calc
// which has greater magnitude ? Used for sign calc
reg a_gt_b3;
reg a_gt_b3;
reg resZero3;
reg resZero3;
reg [FMSB+1:0] mfs3;
reg [FMSB+1:0] mfs3;
 
wire aNan3, bNan3;
 
 
delay1 #(EMSB+1)  dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
delay1 #(EMSB+1)  dxa3(.clk(clk), .ce(ce), .i(xa2), .o(xa3));
delay1 #(EMSB+1)  dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
delay1 #(EMSB+1)  dxb3(.clk(clk), .ce(ce), .i(xb2), .o(xb3));
delay1 #(1) dxabInf2(.clk(clk), .ce(ce), .i(xabInf2), .o(xabInf3));
delay1 #(1) dxabInf2(.clk(clk), .ce(ce), .i(xabInf2), .o(xabInf3));
delay1 #(1) dxagtxb2(.clk(clk), .ce(ce), .i(xa_gt_xb2), .o(xa_gt_xb3));
delay1 #(1) dxagtxb2(.clk(clk), .ce(ce), .i(xa_gt_xb2), .o(xa_gt_xb3));
delay2 #(1) dsa2(.clk(clk), .ce(ce), .i(sa1), .o(sa3));
delay2 #(1) dsa2(.clk(clk), .ce(ce), .i(sa1), .o(sa3));
delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
delay2 #(1) dsb2(.clk(clk), .ce(ce), .i(sb1), .o(sb3));
delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
delay2 #(1) dop2(.clk(clk), .ce(ce), .i(op1), .o(op3));
delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
delay3 #(3) drm2(.clk(clk), .ce(ce), .i(rm), .o(rm3));
 
delay2 #(1) dan2(.clk(clk), .ce(ce), .i(aNan1), .o(aNan3));
 
delay2 #(1) dbn2(.clk(clk), .ce(ce), .i(bNan1), .o(bNan3));
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
        if (ce) a_gt_b3 <= xa_gt_xb2 || var2;
// Find out if the result will be zero.
// Find out if the result will be zero.
always @(posedge clk)
always @(posedge clk)
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        if (ce) xo4 <= xabInf3 ? xa3 : resZero3 ? {EMSB+1{1'b0}} : xa_gt_xb3 ? xa3 : xb3;
        if (ce) xo4 <= xabInf3 ? xa3 : resZero3 ? {EMSB+1{1'b0}} : xa_gt_xb3 ? xa3 : xb3;
 
 
// Compute output sign
// Compute output sign
always @(posedge clk)
always @(posedge clk)
if (ce)
if (ce)
        case ({resZero3,sa3,op3,sb3})   // synopsys full_case parallel_case
        casez ({aNan3,bNan3,resZero3,sa3,op3,sb3})      // synopsys full_case parallel_case
        4'b0000: so4 <= 0;                       // + + + = +
        6'b10????: so4 <= sa3;
        4'b0001: so4 <= !a_gt_b3;       // + + - = sign of larger
        6'b01????: so4 <= sb3;
        4'b0010: so4 <= !a_gt_b3;       // + - + = sign of larger
        6'b11????: so4 <= a_gt_b3 ? sa3 : sb3;
        4'b0011: so4 <= 0;                       // + - - = +
        6'b000000: so4 <= 0;                     // + + + = +
        4'b0100: so4 <= a_gt_b3;                // - + + = sign of larger
        6'b000001: so4 <= a_gt_b3 ? 1'b0 : 1'b1;        // + + - = sign of larger
        4'b0101: so4 <= 1;                      // - + - = -
        6'b000010: so4 <= a_gt_b3 ? 1'b0 : 1'b1;        // + - + = sign of larger
        4'b0110: so4 <= 1;                      // - - + = -
        6'b000011: so4 <= 0;                     // + - - = +
        4'b0111: so4 <= a_gt_b3;                // - - - = sign of larger
        6'b000100: so4 <= a_gt_b3 ? 1'b1 : 1'b0;                // - + + = sign of larger
        4'b1000: so4 <= 0;                       //  A +  B, sign = +
        6'b000101: so4 <= 1;                    // - + - = -
        4'b1001: so4 <= rm3==3'd3;              //  A + -B, sign = + unless rounding down
        6'b000110: so4 <= 1;                    // - - + = -
        4'b1010: so4 <= rm3==3'd3;              //  A -  B, sign = + unless rounding down
        6'b000111: so4 <= a_gt_b3 ? 1'b1 : 1'b0;                // - - - = sign of larger
        4'b1011: so4 <= 0;                       // +A - -B, sign = +
 
        4'b1100: so4 <= rm3==3'd3;              // -A +  B, sign = + unless rounding down
        6'b001000: so4 <= 0;                     //  A +  B, sign = +
        4'b1101: so4 <= 1;                      // -A + -B, sign = -
        6'b001001: so4 <= rm3==3'd3;            //  A + -B, sign = + unless rounding down
        4'b1110: so4 <= 1;                      // -A - +B, sign = -
        6'b001010: so4 <= rm3==3'd3;            //  A -  B, sign = + unless rounding down
        4'b1111: so4 <= rm3==3'd3;              // -A - -B, sign = + unless rounding down
        6'b001011: so4 <= 0;                     // +A - -B, sign = +
 
        6'b001100: so4 <= rm3==3'd3;            // -A +  B, sign = + unless rounding down
 
        6'b001101: so4 <= 1;                    // -A + -B, sign = -
 
        6'b001110: so4 <= 1;                    // -A - +B, sign = -
 
        6'b001111: so4 <= rm3==3'd3;            // -A - -B, sign = + unless rounding down
        endcase
        endcase
 
 
always @(posedge clk)
always @(posedge clk)
if (ce) xdif4 <= xdiff3 > FMSB+3 ? FMSB+3 : xdiff3;
if (ce) xdif4 <= xdiff3 > FMSB+3 ? FMSB+3 : xdiff3;
delay1 #(FMSB+2) dmsf3(.clk(clk), .ce(ce), .i(mfs3), .o(mfs4));
delay1 #(FMSB+2) dmsf3(.clk(clk), .ce(ce), .i(mfs3), .o(mfs4));
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delay1 #(EMSB+1) dxdif4(.clk(clk), .ce(ce), .i(xdif4), .o(xdif5) );
delay1 #(EMSB+1) dxdif4(.clk(clk), .ce(ce), .i(xdif4), .o(xdif5) );
delay1 #(FMSB+2) dmsf4(.clk(clk), .ce(ce), .i(mfs4), .o(mfs5));
delay1 #(FMSB+2) dmsf4(.clk(clk), .ce(ce), .i(mfs4), .o(mfs5));
 
 
generate
generate
begin
begin
if (FPWID+`EXTRA_BITS==128)
if (FPWID==128)
    redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor128 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==96)
else if (FPWID==96)
    redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor96 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==84)
else if (FPWID==84)
    redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor84 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==80)
else if (FPWID==80)
    redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor80 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==64)
else if (FPWID==64)
    redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor64 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==40)
else if (FPWID==40)
    redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor40 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==32)
else if (FPWID==32)
    redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
    redor32 u1 (.a(xdif4), .b({mfs4,2'b0}), .o(sticky) );
end
end
endgenerate
endgenerate
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
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always @(posedge clk)
always @(posedge clk)
if (ce)
if (ce)
        casez({anbInf9,aNan9,bNan9,xinf9})
        casez({anbInf9,aNan9,bNan9,xinf9})
        4'b1???:        mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}};       // inf +/- inf - generate QNaN on subtract, inf on add
        4'b1???:        mo <= {1'b0,op9,{FMSB-1{1'b0}},op9,{FMSB{1'b0}}};       // inf +/- inf - generate QNaN on subtract, inf on add
        4'b01??:        mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}};      // set MSB of Nan to convert to quiet
        4'b01??:        mo <= {1'b1,1'b1,fracta9[FMSB-1:0],{FMSB+1{1'b0}}};      // Set MSB of Nan to convert to quiet
        4'b001?:        mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
        4'b001?:        mo <= {1'b1,1'b1,fractb9[FMSB-1:0],{FMSB+1{1'b0}}};
        4'b0001:        mo <= 1'd0;             // exponent hit infinity -> force mantissa to zero
        4'b0001:        mo <= 1'd0;             // exponent hit infinity -> force mantissa to zero
        default:        mo <= {mab9,{FMSB-1{1'b0}}};    // mab has an extra lead bit and two trailing bits
        default:        mo <= {mab9,{FMSB-1{1'b0}}};    // mab has an extra lead bit and two trailing bits
        endcase
        endcase
 
 
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wire [EX:0] o1;
wire [EX:0] o1;
wire [MSB+3:0] fpn0;
wire [MSB+3:0] fpn0;
 
 
fpAddsub  #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
fpAddsub  #(FPWID) u1 (clk, ce, rm, op, a, b, o1);
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(1'b0), .i(o1), .o(fpn0) );
fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(1'b0), .i(o1), .o(fpn0) );
fpRound         #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
fpRound         #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
 
 
endmodule
endmodule
 
 
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