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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpCompare.sv] - Diff between revs 29 and 48

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2007-2019  Robert Finch, Waterloo
//   \\__/ o\    (C) 2007-2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      fpCompare.sv
//      fpCompare.sv
//    - floating point comparison unit
//    - floating point comparison unit
//    - parameterized FPWIDth
//    - parameterized width
//    - IEEE 754 representation
//    - IEEE 754 representation
//
//
//
//
// This source file is free software: you can redistribute it and/or modify
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// it under the terms of the GNU Lesser General Public License as published
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// You should have received a copy of the GNU General Public License
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see .
// along with this program.  If not, see .
//
//
// ============================================================================
// ============================================================================
 
 
`include "fpConfig.sv"
import fp::*;
 
 
module fpCompare(a, b, o, nanx);
module fpCompare(a, b, o, nan, snan);
parameter FPWID = 32;
input [FPWID-1:0] a, b;
`include "fpSize.sv"
 
 
 
input [MSB:0] a, b;
 
output [4:0] o;
output [4:0] o;
reg [4:0] o;
reg [4:0] o;
output nanx;
output nan;
 
output snan;
 
 
// Decompose the operands
// Decompose the operands
wire sa;
wire sa;
wire sb;
wire sb;
wire [EMSB:0] xa;
wire [EMSB:0] xa;
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wire [FMSB:0] ma;
wire [FMSB:0] ma;
wire [FMSB:0] mb;
wire [FMSB:0] mb;
wire az, bz;
wire az, bz;
wire nan_a, nan_b;
wire nan_a, nan_b;
 
 
fpDecomp #(FPWID) u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .qnan(), .snan(), .nan(nan_a) );
fpDecomp u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .qnan(), .snan(), .nan(nan_a) );
fpDecomp #(FPWID) u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .qnan(), .snan(), .nan(nan_b) );
fpDecomp u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .qnan(), .snan(), .nan(nan_b) );
 
 
wire unordered = nan_a | nan_b;
wire unordered = nan_a | nan_b;
 
 
wire eq = !unordered & ((az & bz) || (a==b));  // special test for zero
wire eq = !unordered & ((az & bz) || (a==b));  // special test for zero
wire gt1 = {xa,ma} > {xb,mb};
wire gt1 = {xa,ma} > {xb,mb};
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        o[4] = unordered;
        o[4] = unordered;
end
end
 
 
// an unorder comparison will signal a nan exception
// an unorder comparison will signal a nan exception
//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
assign nanx = 1'b0;
assign nan = nan_a|nan_b;
 
assign snan = (nan_a & ~ma[FMSB]) | (nan_b & ~mb[FMSB]);
 
 
endmodule
endmodule

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