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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2019-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// Uncomment the following to generate code with minimum latency.
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// Uncomment the following to generate code with minimum latency.
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// Minimum latency is zero meaning all the clock edges are removed and
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// Minimum latency is zero meaning all the clock edges are removed and
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// calculations are performed in one long clock cycle. This will result in
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// calculations are performed in one long clock cycle. This will result in
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// the maximum clock rate being really low.
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// the maximum clock rate being really low.
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//`define MIN_LATENCY 1'b1
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`define MIN_LATENCY 1'b1
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// Number of bits extra beyond specified FPWIDth for calculation results
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// Number of bits extra beyond specified FPWIDth for calculation results
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// should be a multiple of four
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// should be a multiple of four
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`define EXTRA_BITS 0
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`define EXTRA_BITS 0
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`define FPWID 80
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// This file contains defintions for fields to ease dealing with different fp
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// FPWIDths. Some of the code still needs to be modified to support FPWIDths
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// other than standard 32,64 or 80 bit.
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`define MSB (`FPWID-1)
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`define EMSB (`FPWID==128 ? 14 : `FPWID==96 ? 14 : `FPWID==80 ? 14 : `FPWID==64 ? 10 : `FPWID==52 ? 10 : `FPWID==48 ? 10 : `FPWID==44 ? 10 : `FPWID==42 ? 10 : `FPWID==40 ? 9 : `FPWID==32 ? 7 : `FPWID==24 ? 6 : 49)
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`define FMSB (`FPWID==128 ? (111) : `FPWID==96 ? (79) : `FPWID==80 ? (63) : `FPWID==64 ? (51) : `FPWID==52 ? (39) : `FPWID==48 ? (35) : `FPWID==44 ? (31) : `FPWID==42 ? (29) : `FPWID==40 ? (28) : `FPWID==32 ? (22) : `FPWID==24 ? (15) : (9))
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`define FX ((`FMSB+2)*2) // the MSB of the expanded fraction
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`define EX (`FX + 1 + `EMSB + 1 + 1 - 1)
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// Only uncomment one of the following for the divider
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// radix four has a faster cycle time
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// radix sixteen uses fewer clock cycles
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`define DIV_RADIX4 1'b1
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//`define DIV_RADIX16 1'b1
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