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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpConfig.sv] - Diff between revs 29 and 35

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Rev 29 Rev 35
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`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
//   \\__/ o\    (C) 2019-2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
// This source file is free software: you can redistribute it and/or modify
// This source file is free software: you can redistribute it and/or modify
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// Uncomment the following to generate code with minimum latency.
// Uncomment the following to generate code with minimum latency.
// Minimum latency is zero meaning all the clock edges are removed and
// Minimum latency is zero meaning all the clock edges are removed and
// calculations are performed in one long clock cycle. This will result in
// calculations are performed in one long clock cycle. This will result in
// the maximum clock rate being really low.
// the maximum clock rate being really low.
 
 
//`define MIN_LATENCY           1'b1
`define MIN_LATENCY             1'b1
 
 
// Number of bits extra beyond specified FPWIDth for calculation results
// Number of bits extra beyond specified FPWIDth for calculation results
// should be a multiple of four
// should be a multiple of four
`define EXTRA_BITS              0
`define EXTRA_BITS              0
 
 
 
`define FPWID           80
 
 
 
// This file contains defintions for fields to ease dealing with different fp
 
// FPWIDths. Some of the code still needs to be modified to support FPWIDths
 
// other than standard 32,64 or 80 bit.
 
`define MSB     (`FPWID-1)
 
`define EMSB    (`FPWID==128 ? 14 : `FPWID==96 ? 14 : `FPWID==80 ? 14 : `FPWID==64 ? 10 : `FPWID==52 ? 10 : `FPWID==48 ? 10 : `FPWID==44 ? 10 : `FPWID==42 ? 10 : `FPWID==40 ?  9 : `FPWID==32 ?  7 : `FPWID==24 ?  6 : 49)
 
`define FMSB    (`FPWID==128 ? (111) : `FPWID==96 ? (79) : `FPWID==80 ? (63) : `FPWID==64 ? (51) : `FPWID==52 ? (39) : `FPWID==48 ? (35) : `FPWID==44 ? (31) : `FPWID==42 ? (29) : `FPWID==40 ? (28) : `FPWID==32 ? (22) : `FPWID==24 ? (15) : (9))
 
`define FX              ((`FMSB+2)*2)   // the MSB of the expanded fraction
 
`define EX              (`FX + 1 + `EMSB + 1 + 1 - 1)
 
 
 
// Only uncomment one of the following for the divider
 
// radix four has a faster cycle time
 
// radix sixteen uses fewer clock cycles
 
`define DIV_RADIX4      1'b1
 
//`define DIV_RADIX16   1'b1

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