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wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}}; //2^0 exponent
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wire [EMSB:0] bias = {1'b0,{EMSB{1'b1}}}; //2^0 exponent
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// The following is a template for a quiet nan. (MSB=1)
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// The following is a template for a quiet nan. (MSB=1)
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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wire [FMSB:0] qNaN = {1'b1,{FMSB{1'b0}}};
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// variables
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// variables
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wire [EMSB+2:0] ex1; // sum of exponents
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reg [EMSB+2:0] ex1; // sum of exponents
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`ifndef GOLDSCHMIDT
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`ifndef GOLDSCHMIDT
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wire [(FMSB+FADD)*2-1:0] divo;
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wire [(FMSB+FADD)*2-1:0] divo;
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`else
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`else
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wire [(FMSB+5)*2-1:0] divo;
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wire [(FMSB+5)*2-1:0] divo;
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`endif
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`endif
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// - derive basic information
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// - derive basic information
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// - calculate exponent
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// - calculate exponent
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// - calculate fraction
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// - calculate fraction
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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fpDecomp #(FPWID) u1a (.i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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wire ld1;
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fpDecomp #(FPWID) u1b (.i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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fpDecompReg #(FPWID) u1a (.clk(clk), .ce(ce), .i(a), .sgn(sa), .exp(xa), .fract(fracta), .xz(a_dn), .vz(az), .inf(aInf), .nan(aNan) );
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fpDecompReg #(FPWID) u1b (.clk(clk), .ce(ce), .i(b), .sgn(sb), .exp(xb), .fract(fractb), .xz(b_dn), .vz(bz), .inf(bInf), .nan(bNan) );
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delay1 #(1) u5 (.clk(clk), .ce(ce), .i(ld), .o(ld1));
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// Compute the exponent.
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// Compute the exponent.
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// - correct the exponent for denormalized operands
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// - correct the exponent for denormalized operands
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// - adjust the difference by the bias (add 127)
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// - adjust the difference by the bias (add 127)
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// - also factor in the different decimal position for division
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// - also factor in the different decimal position for division
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reg [EMSB+2:0] ex1a;
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always @(posedge clk)
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if (ce) ex1a = (xa|a_dn) - (xb|b_dn) + bias;
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`ifndef GOLDSCHMIDT
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`ifndef GOLDSCHMIDT
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB + (FADD-1) - lzcnt - 8'd1;
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always @(posedge clk)
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if (ce) ex1 = ex1a + FMSB + (FADD-1) - lzcnt - 8'd1;
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`else
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`else
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assign ex1 = (xa|a_dn) - (xb|b_dn) + bias + FMSB - lzcnt + 8'd4;
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if (ce) ex1 = ex1a + FMSB - lzcnt + 8'd4;
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`endif
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`endif
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// check for exponent underflow/overflow
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// check for exponent underflow/overflow
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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// Perform divide
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// Perform divide
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// Divider width must be a multiple of four
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// Divider width must be a multiple of four
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`ifndef GOLDSCHMIDT
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`ifndef GOLDSCHMIDT
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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`ifdef DIV_RADIX4
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fpdivr4 #(FMSB+FADD) u2 (.clk(clk), .ld(ld1), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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`endif
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`ifdef DIV_RADIX16
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld1), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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`endif
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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reg [(FMSB+FADD)*2-1:0] divo1;
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reg [(FMSB+FADD)*2-1:0] divo1, divo2;
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reg [7:0] lzcnts;
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always @(posedge clk)
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if (ce) lzcnts = lzcnt - 2;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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if (ce) divo2 = divo[(FMSB+FADD)*2-1:0];
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always @(posedge clk)
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if (ce) divo1 = divo2 << lzcnts;
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`else
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`else
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DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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u2 (.rst(rst), .clk(clk), .ld(ld1), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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reg [(FMSB+6)*2+1:0] divo1;
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reg [(FMSB+6)*2+1:0] divo1, divo2;
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always @(posedge clk)
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if (ce) divo2 = divo;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) divo1 =
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if (ce) divo1 =
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lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
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lzcnt > 8'd5 ? divo2 << (lzcnt-8'd6) :
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divo >> (8'd6-lzcnt);
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divo2 >> (8'd6-lzcnt);
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;
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;
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`endif
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`endif
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delay1 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done2));
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delay2 #(1) u3 (.clk(clk), .ce(ce), .i(done1), .o(done2));
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delay2 #(1) u4 (.clk(clk), .ce(ce), .i(done1), .o(done));
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delay3 #(1) u4 (.clk(clk), .ce(ce), .i(done1), .o(done));
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// determine when a NaN is output
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// determine when a NaN is output
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wire qNaNOut = (az&bz)|(aInf&bInf);
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wire qNaNOut = (az&bz)|(aInf&bInf);
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