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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpDiv.v
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// fpDiv.v
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// - floating point divider
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// - floating point divider
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// - parameterized FPWIDth
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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`include "fp_defines.v"
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`include "fp_defines.v"
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//`define GOLDSCHMIDT 1'b1
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//`define GOLDSCHMIDT 1'b1
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module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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module fpDiv(rst, clk, clk4x, ce, ld, op, a, b, o, done, sign_exe, overflow, underflow);
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parameter FPWID = 128;
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parameter FPWID = 64;
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`include "fpSize.sv"
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`include "fpSize.sv"
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// FADD is a constant that makes the divider FPWIDth a multiple of four and includes eight extra bits.
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// FADD is a constant that makes the divider width a multiple of four and includes eight extra bits.
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localparam FADD = FPWID+`EXTRA_BITS==128 ? 9 :
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localparam FADD = FPWID==128 ? 9 :
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FPWID+`EXTRA_BITS==96 ? 9 :
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FPWID==96 ? 9 :
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FPWID+`EXTRA_BITS==84 ? 9 :
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FPWID==84 ? 9 :
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FPWID+`EXTRA_BITS==80 ? 9 :
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FPWID==80 ? 9 :
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FPWID+`EXTRA_BITS==64 ? 13 :
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FPWID==64 ? 13 :
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FPWID+`EXTRA_BITS==52 ? 9 :
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FPWID==52 ? 9 :
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FPWID+`EXTRA_BITS==48 ? 10 :
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FPWID==48 ? 10 :
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FPWID+`EXTRA_BITS==44 ? 9 :
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FPWID==44 ? 9 :
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FPWID+`EXTRA_BITS==42 ? 11 :
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FPWID==42 ? 11 :
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FPWID+`EXTRA_BITS==40 ? 8 :
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FPWID==40 ? 8 :
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FPWID+`EXTRA_BITS==32 ? 10 :
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FPWID==32 ? 10 :
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FPWID+`EXTRA_BITS==24 ? 9 : 11;
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FPWID==24 ? 9 : 11;
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input rst;
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input rst;
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input clk;
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input clk;
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input clk4x;
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input clk4x;
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input ce;
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input ce;
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// check for exponent underflow/overflow
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// check for exponent underflow/overflow
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire under = ex1[EMSB+2]; // MSB set = negative exponent
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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wire over = (&ex1[EMSB:0] | ex1[EMSB+1]) & !ex1[EMSB+2];
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// Perform divide
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// Perform divide
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// Divider FPWIDth must be a multiple of four
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// Divider width must be a multiple of four
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`ifndef GOLDSCHMIDT
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`ifndef GOLDSCHMIDT
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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fpdivr16 #(FMSB+FADD) u2 (.clk(clk), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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//fpdivr2 #(FMSB+FADD) u2 (.clk4x(clk4x), .ld(ld), .a({3'b0,fracta,8'b0}), .b({3'b0,fractb,8'b0}), .q(divo), .r(), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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wire [(FMSB+FADD)*2-1:0] divo1 = divo[(FMSB+FADD)*2-1:0] << (lzcnt-2);
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`else
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`else
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DivGoldschmidt #(.FPWID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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DivGoldschmidt #(.WID(FMSB+6),.WHOLE(1),.POINTS(FMSB+5))
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u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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u2 (.rst(rst), .clk(clk), .ld(ld), .a({fracta,4'b0}), .b({fractb,4'b0}), .q(divo), .done(done1), .lzcnt(lzcnt));
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wire [(FMSB+6)*2+1:0] divo1 =
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wire [(FMSB+6)*2+1:0] divo1 =
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lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
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lzcnt > 8'd5 ? divo << (lzcnt-8'd6) :
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divo >> (8'd6-lzcnt);
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divo >> (8'd6-lzcnt);
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;
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;
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5'b00001: xo <= 1'd0; // underflow
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5'b00001: xo <= 1'd0; // underflow
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default: xo <= ex1; // normal or underflow: passthru neg. exp. for normalization
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default: xo <= ex1; // normal or underflow: passthru neg. exp. for normalization
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endcase
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endcase
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casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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casez({aNan,bNan,qNaNOut,bInf,bz,over,aInf&bInf,az&bz})
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8'b1???????: mo <= {1'b1,1'b1,a[FMSB-1:0],{FMSB+1{1'b0}}};
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8'b1???????: mo <= {1'b1,a[FMSB:0],{FMSB+1{1'b0}}};
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8'b01??????: mo <= {1'b1,1'b1,b[FMSB-1:0],{FMSB+1{1'b0}}};
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8'b01??????: mo <= {1'b1,b[FMSB:0],{FMSB+1{1'b0}}};
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8'b001?????: mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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8'b001?????: mo <= {1'b1,qNaN[FMSB:0]|{aInf,1'b0}|{az,bz},{FMSB+1{1'b0}}};
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8'b0001????: mo <= 1'd0; // div by inf
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8'b0001????: mo <= 1'd0; // div by inf
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8'b00001???: mo <= 1'd0; // div by zero
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8'b00001???: mo <= 1'd0; // div by zero
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8'b000001??: mo <= 1'd0; // Inf exponent
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8'b000001??: mo <= 1'd0; // Inf exponent
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8'b0000001?: mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}}; // infinity / infinity
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8'b0000001?: mo <= {1'b1,qNaN|`QINFDIV,{FMSB+1{1'b0}}}; // infinity / infinity
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end
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end
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endmodule
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endmodule
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module fpDivnr(rst, clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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module fpDivnr(rst, clk, clk4x, ce, ld, op, a, b, o, rm, done, sign_exe, inf, overflow, underflow);
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parameter FPWID=32;
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parameter FPWID=64;
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`include "fpSize.sv"
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`include "fpSize.sv"
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input rst;
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input rst;
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input clk;
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input clk;
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input clk4x;
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input clk4x;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire sign_exe1, inf1, overflow1, underflow1;
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wire [MSB+3:0] fpn0;
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wire [MSB+3:0] fpn0;
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wire done1;
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wire done1;
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fpDiv #(FPWID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpDiv #(FPWID) u1 (rst, clk, clk4x, ce, ld, op, a, b, o1, done1, sign_exe1, overflow1, underflow1);
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under(underflow1), .i(o1), .o(fpn0) );
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fpNormalize #(FPWID) u2(.clk(clk), .ce(ce), .under_i(underflow1), .i(o1), .o(fpn0) );
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fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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fpRound #(FPWID) u3(.clk(clk), .ce(ce), .rm(rm), .i(fpn0), .o(o) );
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u4(.clk(clk), .ce(ce), .i(sign_exe1), .o(sign_exe));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u5(.clk(clk), .ce(ce), .i(inf1), .o(inf));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u6(.clk(clk), .ce(ce), .i(overflow1), .o(overflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay2 #(1) u7(.clk(clk), .ce(ce), .i(underflow1), .o(underflow));
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delay2 #(1) u8(.clk(clk), .ce(ce), .i(done1), .o(done));
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vtdl #(1) u8(.clk(clk), .ce(ce), .a(4'd13), .d(done1), .q(done));
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endmodule
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endmodule
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