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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpFMA.sv] - Diff between revs 48 and 58

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// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2019-2020  Robert Finch, Waterloo
//   \\__/ o\    (C) 2019-2021  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch@finitron.ca
//     \/_//     robfinch@finitron.ca
//       ||
//       ||
//
//
//      fpFMA.sv
//      fpFMA.sv
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//              - can issue every clock cycle
//              - can issue every clock cycle
//              - parameterized FPWIDth
//              - parameterized FPWIDth
//              - IEEE 754 representation
//              - IEEE 754 representation
//
//
//
//
// This source file is free software: you can redistribute it and/or modify
// BSD 3-Clause License
// it under the terms of the GNU Lesser General Public License as published
// Redistribution and use in source and binary forms, with or without
// by the Free Software Foundation, either version 3 of the License, or
// modification, are permitted provided that the following conditions are met:
// (at your option) any later version.
 
//
//
// This source file is distributed in the hope that it will be useful,
// 1. Redistributions of source code must retain the above copyright notice, this
// but WITHOUT ANY WARRANTY; without even the implied warranty of
//    list of conditions and the following disclaimer.
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 
// GNU General Public License for more details.
 
//
//
// You should have received a copy of the GNU General Public License
// 2. Redistributions in binary form must reproduce the above copyright notice,
// along with this program.  If not, see .
//    this list of conditions and the following disclaimer in the documentation
 
//    and/or other materials provided with the distribution.
 
//
 
// 3. Neither the name of the copyright holder nor the names of its
 
//    contributors may be used to endorse or promote products derived from
 
//    this software without specific prior written permission.
 
//
 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
 
 
import fp::*;
import fp::*;
 
 
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wire sticky, sticky12;
wire sticky, sticky12;
wire [FX:0] mfs12;
wire [FX:0] mfs12;
wire [7:0] xdif12;
wire [7:0] xdif12;
 
 
 
redorN #(.BSIZE(FX+1)) uredor1 (.a({1'b0,xdif11+FMSB}), .b(mfs), .o(sticky));
 
/*
generate
generate
begin
begin
if (FPWID==128)
if (FPWID==128)
  redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
  redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
else if (FPWID==96)
else if (FPWID==96)
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        $finish;
        $finish;
  end
  end
end
end
end
end
endgenerate
endgenerate
 
*/
 
 
// register inputs to shifter and shift
// register inputs to shifter and shift
delay1 #(1)    u122(.clk(clk), .ce(ce), .i(sticky), .o(sticky12) );
delay1 #(1)    u122(.clk(clk), .ce(ce), .i(sticky), .o(sticky12) );
delay1 #(8)    u123(.clk(clk), .ce(ce), .i(xdif11),   .o(xdif12) );
delay1 #(8)    u123(.clk(clk), .ce(ce), .i(xdif11),   .o(xdif12) );
delay2 #(FX+1) u124(.clk(clk), .ce(ce), .i(mfs), .o(mfs12) );
delay2 #(FX+1) u124(.clk(clk), .ce(ce), .i(mfs), .o(mfs12) );

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