| Line 28... |
Line 28... |
// ============================================================================
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// ============================================================================
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`include "fpConfig.sv"
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`include "fpConfig.sv"
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module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
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module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
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parameter FPWID = 32;
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parameter FPWID = 128;
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parameter MUL_LATENCY = FPWID==128 ? 16 :
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FPWID==80 ? 16 :
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FPWID==64 ? 16 :
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FPWID==32 ? 5 :
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1;
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`include "fpSize.sv"
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`include "fpSize.sv"
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input clk;
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input clk;
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input ce;
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input ce;
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input op; // operation 0 = add, 1 = subtract
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input op; // operation 0 = add, 1 = subtract
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| Line 112... |
Line 117... |
// -a - -b = sub, so of larger
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// -a - -b = sub, so of larger
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always @(posedge clk)
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always @(posedge clk)
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if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
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if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
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reg [FX:0] fract5;
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wire [FX:0] fract17;
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generate
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generate begin : gMults
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if (FPWID+`EXTRA_BITS==84) begin
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// 16 clocks for multiply
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reg [33:0] p00,p01,p02,p03;
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if (FPWID==128) begin
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reg [33:0] p10,p11,p12,p13;
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mult114x114 umul1 (clk, ce, {1'b0,fracta1}, {1'b0,fractb1}, fract17[FX-1:0]);
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reg [33:0] p20,p21,p22,p23;
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assign fract17[FX] = 1'b0;
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reg [33:0] p30,p31,p32,p33;
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end
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reg [135:0] fract3a;
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else if (FPWID==80) begin
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reg [135:0] fract3b;
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mult64x64 umul2 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
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reg [135:0] fract3c;
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assign fract17[FX] = 1'b0;
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reg [135:0] fract3d;
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end
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reg [135:0] fract4a;
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else if (FPWID==64) begin
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reg [135:0] fract4b;
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mult53x53 umul3 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
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assign fract17[FX] = 1'b0;
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always @(posedge clk)
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end
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if (ce) begin
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else if (FPWID==32) begin
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p00 <= fracta1[16: 0] * fractb1[16: 0];
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mult24x24 umul4 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
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p01 <= fracta1[33:17] * fractb1[16: 0];
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assign fract17[FX] = 1'b0;
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p02 <= fracta1[50:34] * fractb1[16: 0];
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p03 <= fracta1[67:51] * fractb1[16: 0];
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p10 <= fracta1[16: 0] * fractb1[33:17];
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p11 <= fracta1[33:17] * fractb1[33:17];
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p12 <= fracta1[50:34] * fractb1[33:17];
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p13 <= fracta1[67:51] * fractb1[33:17];
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p20 <= fracta1[16: 0] * fractb1[50:34];
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p21 <= fracta1[33:17] * fractb1[50:34];
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p22 <= fracta1[50:34] * fractb1[50:34];
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p23 <= fracta1[67:51] * fractb1[50:34];
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p30 <= fracta1[15: 0] * fractb1[67:51];
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p31 <= fracta1[31:16] * fractb1[67:51];
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p32 <= fracta1[47:32] * fractb1[67:51];
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p33 <= fracta1[63:48] * fractb1[67:51];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p33,p31,p20,p00};
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fract3b <= {p32,p12,p10,17'b0} + {p23,p03,p01,17'b0};
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fract3c <= {p22,p11,34'b0} + {p13,p02,34'b0};
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fract3d <= {p12,51'b0} + {p03,51'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4a <= fract3a + fract3b;
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fract4b <= fract3c + fract3d;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4a + fract4b;
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end
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end
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else if (FPWID+`EXTRA_BITS==80) begin
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reg [31:0] p00,p01,p02,p03;
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reg [31:0] p10,p11,p12,p13;
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reg [31:0] p20,p21,p22,p23;
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reg [31:0] p30,p31,p32,p33;
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reg [127:0] fract3a;
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reg [127:0] fract3b;
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reg [127:0] fract3c;
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reg [127:0] fract3d;
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reg [127:0] fract4a;
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reg [127:0] fract4b;
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always @(posedge clk)
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if (ce) begin
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p00 <= fracta1[15: 0] * fractb1[15: 0];
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p01 <= fracta1[31:16] * fractb1[15: 0];
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p02 <= fracta1[47:32] * fractb1[15: 0];
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p03 <= fracta1[63:48] * fractb1[15: 0];
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p10 <= fracta1[15: 0] * fractb1[31:16];
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p11 <= fracta1[31:16] * fractb1[31:16];
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p12 <= fracta1[47:32] * fractb1[31:16];
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p13 <= fracta1[63:48] * fractb1[31:16];
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p20 <= fracta1[15: 0] * fractb1[47:32];
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p21 <= fracta1[31:16] * fractb1[47:32];
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p22 <= fracta1[47:32] * fractb1[47:32];
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p23 <= fracta1[63:48] * fractb1[47:32];
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p30 <= fracta1[15: 0] * fractb1[63:48];
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p31 <= fracta1[31:16] * fractb1[63:48];
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p32 <= fracta1[47:32] * fractb1[63:48];
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p33 <= fracta1[63:48] * fractb1[63:48];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p33,p31,p20,p00};
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fract3b <= {p32,p12,p10,16'b0} + {p23,p03,p01,16'b0};
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fract3c <= {p22,p11,32'b0} + {p13,p02,32'b0};
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fract3d <= {p12,48'b0} + {p03,48'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4a <= fract3a + fract3b;
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fract4b <= fract3c + fract3d;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4a + fract4b;
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end
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end
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else if (FPWID+`EXTRA_BITS==64) begin
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reg [35:0] p00,p01,p02;
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reg [35:0] p10,p11,p12;
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reg [35:0] p20,p21,p22;
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reg [71:0] fract3a;
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reg [89:0] fract3b;
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reg [107:0] fract3c;
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reg [108:0] fract4a;
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reg [108:0] fract4b;
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always @(posedge clk)
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if (ce) begin
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p00 <= fracta1[17: 0] * fractb1[17: 0];
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p01 <= fracta1[35:18] * fractb1[17: 0];
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p02 <= fracta1[52:36] * fractb1[17: 0];
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p10 <= fracta1[17: 0] * fractb1[35:18];
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p11 <= fracta1[35:18] * fractb1[35:18];
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p12 <= fracta1[52:36] * fractb1[35:18];
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p20 <= fracta1[17: 0] * fractb1[52:36];
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p21 <= fracta1[35:18] * fractb1[52:36];
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p22 <= fracta1[52:36] * fractb1[52:36];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p02,p00};
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fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
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fract3c <= {p22,p20,36'b0} + {p11,36'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4a <= fract3a + fract3b;
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fract4b <= fract3c;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4a + fract4b;
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end
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end
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else if (FPWID+`EXTRA_BITS==40) begin
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reg [27:0] p00,p01,p02;
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reg [27:0] p10,p11,p12;
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reg [27:0] p20,p21,p22;
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reg [79:0] fract3a;
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reg [79:0] fract3b;
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reg [79:0] fract3c;
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reg [79:0] fract4a;
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reg [79:0] fract4b;
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always @(posedge clk)
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if (ce) begin
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p00 <= fracta1[13: 0] * fractb1[13: 0];
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p01 <= fracta1[27:14] * fractb1[13: 0];
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p02 <= fracta1[39:28] * fractb1[13: 0];
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p10 <= fracta1[13: 0] * fractb1[27:14];
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p11 <= fracta1[27:14] * fractb1[27:14];
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p12 <= fracta1[39:28] * fractb1[27:14];
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p20 <= fracta1[13: 0] * fractb1[39:28];
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p21 <= fracta1[27:14] * fractb1[39:28];
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p22 <= fracta1[39:28] * fractb1[39:28];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p02,p00};
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fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
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fract3c <= {p22,p20,36'b0} + {p11,36'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4a <= fract3a + fract3b;
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fract4b <= fract3c;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4a + fract4b;
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end
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end
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else if (FPWID+`EXTRA_BITS==32) begin
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reg [23:0] p00,p01,p02;
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reg [23:0] p10,p11,p12;
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reg [23:0] p20,p21,p22;
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reg [63:0] fract3a;
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reg [63:0] fract3b;
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reg [63:0] fract4;
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always @(posedge clk)
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if (ce) begin
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p00 <= fracta1[11: 0] * fractb1[11: 0];
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p01 <= fracta1[23:12] * fractb1[11: 0];
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p10 <= fracta1[11: 0] * fractb1[23:12];
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p11 <= fracta1[23:12] * fractb1[23:12];
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end
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always @(posedge clk)
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if (ce) begin
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fract3a <= {p11,p00};
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fract3b <= {p01,12'b0} + {p10,12'b0};
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end
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always @(posedge clk)
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if (ce) begin
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fract4 <= fract3a + fract3b;
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end
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always @(posedge clk)
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if (ce) begin
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fract5 <= fract4;
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end
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end
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end
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else begin
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else begin
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reg [FX:0] p00;
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reg [FX:0] fract17a;
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reg [FX:0] fract3;
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reg [FX:0] fract4;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) fract17a <= fracta1 * fractb1;
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p00 <= fracta1 * fractb1;
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assign fract17 = fract17a;
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end
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end
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always @(posedge clk)
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if (ce)
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fract3 <= p00;
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always @(posedge clk)
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if (ce)
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fract4 <= fract3;
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always @(posedge clk)
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if (ce)
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fract5 <= fract4;
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end
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end
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endgenerate
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endgenerate
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #3
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// Clock #3
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| Line 372... |
Line 177... |
// Sum partial products (above)
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// Sum partial products (above)
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// compute multiplier overflow and underflow
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// compute multiplier overflow and underflow
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Status
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// Status
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reg under5;
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wire under5;
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reg over5;
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wire over5;
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reg [EMSB+2:0] ex5;
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wire [EMSB+2:0] ex5;
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reg [EMSB:0] xc5;
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wire [EMSB:0] xc5;
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wire aInf5, bInf5;
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wire aInf5, bInf5;
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wire aNan5, bNan5;
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wire aNan5, bNan5;
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wire qNaNOut5;
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wire qNaNOut5;
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always @(posedge clk)
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vtdl u5a (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(ex4[EMSB+2]), .q(under5));
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if (ce) under5 <= ex4[EMSB+2];
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vtdl u5b (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d((&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2]), .q(over5));
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always @(posedge clk)
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vtdl #(EMSB+3) u5c (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(ex4), .q(ex5));
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if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2];
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vtdl #(EMSB+1) u5d (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(xc4), .q(xc5));
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always @(posedge clk)
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if (ce) ex5 <= ex4;
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always @(posedge clk)
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if (ce) xc5 <= xc4;
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delay4 u2a (.clk(clk), .ce(ce), .i(aInf1), .o(aInf5) );
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vtdl u2a (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(aInf1), .q(aInf5) );
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delay4 u2b (.clk(clk), .ce(ce), .i(bInf1), .o(bInf5) );
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vtdl u2b (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(bInf1), .q(bInf5) );
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// determine when a NaN is output
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// determine when a NaN is output
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wire [MSB:0] a5,b5;
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wire [MSB:0] a5,b5;
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delay4 u5 (.clk(clk), .ce(ce), .i((aInf1&bz1)|(bInf1&az1)), .o(qNaNOut5) );
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vtdl u5 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d((aInf1&bz1)|(bInf1&az1)), .q(qNaNOut5) );
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delay4 u14 (.clk(clk), .ce(ce), .i(aNan1), .o(aNan5) );
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vtdl u14 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(aNan1), .q(aNan5) );
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delay4 u15 (.clk(clk), .ce(ce), .i(bNan1), .o(bNan5) );
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vtdl u15 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(bNan1), .q(bNan5) );
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delay5 #(MSB+1) u16 (.clk(clk), .ce(ce), .i(a), .o(a5) );
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vtdl #(MSB+1) u16 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(a), .q(a5) );
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delay5 #(MSB+1) u17 (.clk(clk), .ce(ce), .i(b), .o(b5) );
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vtdl #(MSB+1) u17 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(b), .q(b5) );
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #6
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// Clock #6
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// - figure multiplier mantissa output
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// - figure multiplier mantissa output
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// - figure multiplier exponent output
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// - figure multiplier exponent output
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| Line 411... |
Line 212... |
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reg [FX:0] mo6;
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reg [FX:0] mo6;
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reg [EMSB+2:0] ex6;
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reg [EMSB+2:0] ex6;
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reg [EMSB:0] xc6;
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reg [EMSB:0] xc6;
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wire [FMSB+1:0] fractc6;
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wire [FMSB+1:0] fractc6;
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vtdl #(FMSB+2) u61 (.clk(clk), .ce(ce), .a(4'd4), .d(fractc1), .q(fractc6) );
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wire under6;
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vtdl #(FMSB+2) u61 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(fractc1), .q(fractc6) );
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delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
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delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) xc6 <= xc5;
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if (ce) xc6 <= xc5;
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| Line 426... |
Line 228... |
6'b01????: mo6 <= {1'b1,1'b1,b5[FMSB-1:0],{FMSB+1{1'b0}}};
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6'b01????: mo6 <= {1'b1,1'b1,b5[FMSB-1:0],{FMSB+1{1'b0}}};
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6'b001???: mo6 <= {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
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6'b001???: mo6 <= {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
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6'b0001??: mo6 <= 0; // mul inf's
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6'b0001??: mo6 <= 0; // mul inf's
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6'b00001?: mo6 <= 0; // mul inf's
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6'b00001?: mo6 <= 0; // mul inf's
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6'b000001: mo6 <= 0; // mul overflow
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6'b000001: mo6 <= 0; // mul overflow
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default: mo6 <= fract5;
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default: mo6 <= fract17;
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endcase
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endcase
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
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casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
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| Line 460... |
Line 262... |
if (ce) xeq7 <= (ex6=={2'b0,xc6});
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if (ce) xeq7 <= (ex6=={2'b0,xc6});
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always @(posedge clk)
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always @(posedge clk)
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if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
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if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
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always @(posedge clk)
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always @(posedge clk)
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if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
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if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
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vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
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vtdl #(1,32) u71 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(az1), .q(az7));
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vtdl #(1) u72 (.clk(clk), .ce(ce), .a(4'd5), .d(bz1), .q(bz7));
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vtdl #(1,32) u72 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(bz1), .q(bz7));
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vtdl #(1) u73 (.clk(clk), .ce(ce), .a(4'd5), .d(cz1), .q(cz7));
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vtdl #(1,32) u73 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(cz1), .q(cz7));
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vtdl #(1) u74 (.clk(clk), .ce(ce), .a(4'd4), .d(realOp2), .q(realOp7));
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vtdl #(1,32) u74 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(realOp2), .q(realOp7));
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|
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// -----------------------------------------------------------
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// -----------------------------------------------------------
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// Clock #8
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// Clock #8
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// - prep for addition, determine greater operand
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// - prep for addition, determine greater operand
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// - determine if result will be zero
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// - determine if result will be zero
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| Line 483... |
Line 285... |
wire op8;
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wire op8;
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wire sa8, sc8;
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wire sa8, sc8;
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|
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delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
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delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
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delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
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delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
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vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
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vtdl #(1,32) u83 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(xcInf2), .q(xcInf8));
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vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
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vtdl #(3,32) u84 (.clk(clk), .ce(ce), .a(MUL_LATENCY+1), .d(rm), .q(rm8));
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vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
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vtdl #(1,32) u85 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(op1), .q(op8));
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vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd6), .d(sa1 ^ sb1), .q(sa8));
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vtdl #(1,32) u86 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(sa1 ^ sb1), .q(sa8));
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vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd6), .d(sc1), .q(sc8));
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vtdl #(1,32) u87 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(sc1), .q(sc8));
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|
|
always @(posedge clk)
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always @(posedge clk)
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if (ce) ex_gt_xc8 <= ex_gt_xc7;
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if (ce) ex_gt_xc8 <= ex_gt_xc7;
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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| Line 615... |
Line 417... |
wire [FX:0] mfs12;
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wire [FX:0] mfs12;
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wire [7:0] xdif12;
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wire [7:0] xdif12;
|
|
|
generate
|
generate
|
begin
|
begin
|
if (FPWID+`EXTRA_BITS==128)
|
if (FPWID==128)
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redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
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else if (FPWID+`EXTRA_BITS==96)
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else if (FPWID==80)
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redor96 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
|
else if (FPWID+`EXTRA_BITS==84)
|
|
redor84 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
|
else if (FPWID+`EXTRA_BITS==80)
|
|
redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==64)
|
else if (FPWID==64)
|
redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
else if (FPWID+`EXTRA_BITS==32)
|
else if (FPWID==32)
|
redor32 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
redor32 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// register inputs to shifter and shift
|
// register inputs to shifter and shift
|
| Line 747... |
Line 545... |
|
|
|
|
// Multiplier with normalization and rounding.
|
// Multiplier with normalization and rounding.
|
|
|
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, zero, overflow, underflow, inexact);
|
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, zero, overflow, underflow, inexact);
|
parameter FPWID=64;
|
parameter FPWID=128;
|
`include "fpSize.sv"
|
`include "fpSize.sv"
|
|
|
input clk;
|
input clk;
|
input ce;
|
input ce;
|
input op;
|
input op;
|
