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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpFMA.v] - Diff between revs 29 and 32

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Line 28... Line 28...
// ============================================================================
// ============================================================================
 
 
`include "fpConfig.sv"
`include "fpConfig.sv"
 
 
module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
module fpFMA (clk, ce, op, rm, a, b, c, o, under, over, inf, zero);
parameter FPWID = 32;
parameter FPWID = 128;
 
parameter MUL_LATENCY = FPWID==128 ? 16 :
 
                                                                                                FPWID==80 ? 16 :
 
                                                                                                FPWID==64 ? 16 :
 
                                                                                                FPWID==32 ?  5 :
 
                                                                                                1;
`include "fpSize.sv"
`include "fpSize.sv"
 
 
input clk;
input clk;
input ce;
input ce;
input op;               // operation 0 = add, 1 = subtract
input op;               // operation 0 = add, 1 = subtract
Line 112... Line 117...
// -a - -b = sub, so of larger
// -a - -b = sub, so of larger
always @(posedge clk)
always @(posedge clk)
        if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
        if (ce) realOp2 <= op1 ^ (sa1 ^ sb1) ^ sc1;
 
 
 
 
reg [FX:0] fract5;
wire [FX:0] fract17;
generate
generate begin : gMults
if (FPWID+`EXTRA_BITS==84) begin
// 16 clocks for multiply
reg [33:0] p00,p01,p02,p03;
if (FPWID==128) begin
reg [33:0] p10,p11,p12,p13;
        mult114x114 umul1 (clk, ce, {1'b0,fracta1}, {1'b0,fractb1}, fract17[FX-1:0]);
reg [33:0] p20,p21,p22,p23;
        assign fract17[FX] = 1'b0;
reg [33:0] p30,p31,p32,p33;
end
reg [135:0] fract3a;
else if (FPWID==80) begin
reg [135:0] fract3b;
        mult64x64 umul2 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
reg [135:0] fract3c;
        assign fract17[FX] = 1'b0;
reg [135:0] fract3d;
end
reg [135:0] fract4a;
else if (FPWID==64) begin
reg [135:0] fract4b;
        mult53x53 umul3 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
 
        assign fract17[FX] = 1'b0;
        always @(posedge clk)
end
        if (ce) begin
else if (FPWID==32) begin
                p00 <= fracta1[16: 0] * fractb1[16: 0];
        mult24x24 umul4 (.CLK(clk), .CE(ce), .A(fracta1), .B(fractb1), .P(fract17[FX-1:0]));
                p01 <= fracta1[33:17] * fractb1[16: 0];
        assign fract17[FX] = 1'b0;
                p02 <= fracta1[50:34] * fractb1[16: 0];
 
                p03 <= fracta1[67:51] * fractb1[16: 0];
 
 
 
                p10 <= fracta1[16: 0] * fractb1[33:17];
 
                p11 <= fracta1[33:17] * fractb1[33:17];
 
                p12 <= fracta1[50:34] * fractb1[33:17];
 
                p13 <= fracta1[67:51] * fractb1[33:17];
 
 
 
                p20 <= fracta1[16: 0] * fractb1[50:34];
 
                p21 <= fracta1[33:17] * fractb1[50:34];
 
                p22 <= fracta1[50:34] * fractb1[50:34];
 
                p23 <= fracta1[67:51] * fractb1[50:34];
 
 
 
                p30 <= fracta1[15: 0] * fractb1[67:51];
 
                p31 <= fracta1[31:16] * fractb1[67:51];
 
                p32 <= fracta1[47:32] * fractb1[67:51];
 
                p33 <= fracta1[63:48] * fractb1[67:51];
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract3a <= {p33,p31,p20,p00};
 
                fract3b <= {p32,p12,p10,17'b0} + {p23,p03,p01,17'b0};
 
                fract3c <= {p22,p11,34'b0} + {p13,p02,34'b0};
 
                fract3d <= {p12,51'b0} + {p03,51'b0};
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract4a <= fract3a + fract3b;
 
                fract4b <= fract3c + fract3d;
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract5 <= fract4a + fract4b;
 
        end
 
end
 
else if (FPWID+`EXTRA_BITS==80) begin
 
reg [31:0] p00,p01,p02,p03;
 
reg [31:0] p10,p11,p12,p13;
 
reg [31:0] p20,p21,p22,p23;
 
reg [31:0] p30,p31,p32,p33;
 
reg [127:0] fract3a;
 
reg [127:0] fract3b;
 
reg [127:0] fract3c;
 
reg [127:0] fract3d;
 
reg [127:0] fract4a;
 
reg [127:0] fract4b;
 
 
 
        always @(posedge clk)
 
        if (ce) begin
 
                p00 <= fracta1[15: 0] * fractb1[15: 0];
 
                p01 <= fracta1[31:16] * fractb1[15: 0];
 
                p02 <= fracta1[47:32] * fractb1[15: 0];
 
                p03 <= fracta1[63:48] * fractb1[15: 0];
 
 
 
                p10 <= fracta1[15: 0] * fractb1[31:16];
 
                p11 <= fracta1[31:16] * fractb1[31:16];
 
                p12 <= fracta1[47:32] * fractb1[31:16];
 
                p13 <= fracta1[63:48] * fractb1[31:16];
 
 
 
                p20 <= fracta1[15: 0] * fractb1[47:32];
 
                p21 <= fracta1[31:16] * fractb1[47:32];
 
                p22 <= fracta1[47:32] * fractb1[47:32];
 
                p23 <= fracta1[63:48] * fractb1[47:32];
 
 
 
                p30 <= fracta1[15: 0] * fractb1[63:48];
 
                p31 <= fracta1[31:16] * fractb1[63:48];
 
                p32 <= fracta1[47:32] * fractb1[63:48];
 
                p33 <= fracta1[63:48] * fractb1[63:48];
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract3a <= {p33,p31,p20,p00};
 
                fract3b <= {p32,p12,p10,16'b0} + {p23,p03,p01,16'b0};
 
                fract3c <= {p22,p11,32'b0} + {p13,p02,32'b0};
 
                fract3d <= {p12,48'b0} + {p03,48'b0};
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract4a <= fract3a + fract3b;
 
                fract4b <= fract3c + fract3d;
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract5 <= fract4a + fract4b;
 
        end
 
end
 
else if (FPWID+`EXTRA_BITS==64) begin
 
reg [35:0] p00,p01,p02;
 
reg [35:0] p10,p11,p12;
 
reg [35:0] p20,p21,p22;
 
reg [71:0] fract3a;
 
reg [89:0] fract3b;
 
reg [107:0] fract3c;
 
reg [108:0] fract4a;
 
reg [108:0] fract4b;
 
 
 
        always @(posedge clk)
 
        if (ce) begin
 
                p00 <= fracta1[17: 0] * fractb1[17: 0];
 
                p01 <= fracta1[35:18] * fractb1[17: 0];
 
                p02 <= fracta1[52:36] * fractb1[17: 0];
 
                p10 <= fracta1[17: 0] * fractb1[35:18];
 
                p11 <= fracta1[35:18] * fractb1[35:18];
 
                p12 <= fracta1[52:36] * fractb1[35:18];
 
                p20 <= fracta1[17: 0] * fractb1[52:36];
 
                p21 <= fracta1[35:18] * fractb1[52:36];
 
                p22 <= fracta1[52:36] * fractb1[52:36];
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract3a <= {p02,p00};
 
                fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
 
                fract3c <= {p22,p20,36'b0} + {p11,36'b0};
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract4a <= fract3a + fract3b;
 
                fract4b <= fract3c;
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract5 <= fract4a + fract4b;
 
        end
 
end
 
else if (FPWID+`EXTRA_BITS==40) begin
 
reg [27:0] p00,p01,p02;
 
reg [27:0] p10,p11,p12;
 
reg [27:0] p20,p21,p22;
 
reg [79:0] fract3a;
 
reg [79:0] fract3b;
 
reg [79:0] fract3c;
 
reg [79:0] fract4a;
 
reg [79:0] fract4b;
 
        always @(posedge clk)
 
        if (ce) begin
 
                p00 <= fracta1[13: 0] * fractb1[13: 0];
 
                p01 <= fracta1[27:14] * fractb1[13: 0];
 
                p02 <= fracta1[39:28] * fractb1[13: 0];
 
                p10 <= fracta1[13: 0] * fractb1[27:14];
 
                p11 <= fracta1[27:14] * fractb1[27:14];
 
                p12 <= fracta1[39:28] * fractb1[27:14];
 
                p20 <= fracta1[13: 0] * fractb1[39:28];
 
                p21 <= fracta1[27:14] * fractb1[39:28];
 
                p22 <= fracta1[39:28] * fractb1[39:28];
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract3a <= {p02,p00};
 
                fract3b <= {p21,p10,18'b0} + {p12,p01,18'b0};
 
                fract3c <= {p22,p20,36'b0} + {p11,36'b0};
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract4a <= fract3a + fract3b;
 
                fract4b <= fract3c;
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract5 <= fract4a + fract4b;
 
        end
 
end
 
else if (FPWID+`EXTRA_BITS==32) begin
 
reg [23:0] p00,p01,p02;
 
reg [23:0] p10,p11,p12;
 
reg [23:0] p20,p21,p22;
 
reg [63:0] fract3a;
 
reg [63:0] fract3b;
 
reg [63:0] fract4;
 
 
 
        always @(posedge clk)
 
        if (ce) begin
 
                p00 <= fracta1[11: 0] * fractb1[11: 0];
 
                p01 <= fracta1[23:12] * fractb1[11: 0];
 
                p10 <= fracta1[11: 0] * fractb1[23:12];
 
                p11 <= fracta1[23:12] * fractb1[23:12];
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract3a <= {p11,p00};
 
                fract3b <= {p01,12'b0} + {p10,12'b0};
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract4 <= fract3a + fract3b;
 
        end
 
        always @(posedge clk)
 
        if (ce) begin
 
                fract5 <= fract4;
 
        end
 
end
end
else begin
else begin
reg [FX:0] p00;
        reg [FX:0] fract17a;
reg [FX:0] fract3;
 
reg [FX:0] fract4;
 
        always @(posedge clk)
        always @(posedge clk)
    if (ce) begin
                if (ce) fract17a <= fracta1 * fractb1;
        p00 <= fracta1 * fractb1;
        assign fract17 = fract17a;
    end
    end
        always @(posedge clk)
 
    if (ce)
 
        fract3 <= p00;
 
        always @(posedge clk)
 
    if (ce)
 
        fract4 <= fract3;
 
        always @(posedge clk)
 
    if (ce)
 
        fract5 <= fract4;
 
end
end
endgenerate
endgenerate
 
 
// -----------------------------------------------------------
// -----------------------------------------------------------
// Clock #3
// Clock #3
Line 372... Line 177...
// Sum partial products (above)
// Sum partial products (above)
// compute multiplier overflow and underflow
// compute multiplier overflow and underflow
// -----------------------------------------------------------
// -----------------------------------------------------------
 
 
// Status
// Status
reg under5;
wire under5;
reg over5;
wire over5;
reg [EMSB+2:0] ex5;
wire [EMSB+2:0] ex5;
reg [EMSB:0] xc5;
wire [EMSB:0] xc5;
wire aInf5, bInf5;
wire aInf5, bInf5;
wire aNan5, bNan5;
wire aNan5, bNan5;
wire qNaNOut5;
wire qNaNOut5;
 
 
always @(posedge clk)
vtdl u5a (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(ex4[EMSB+2]), .q(under5));
        if (ce) under5 <= ex4[EMSB+2];
vtdl u5b (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d((&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2]), .q(over5));
always @(posedge clk)
vtdl #(EMSB+3) u5c (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(ex4), .q(ex5));
        if (ce) over5 <= (&ex4[EMSB:0] | ex4[EMSB+1]) & !ex4[EMSB+2];
vtdl #(EMSB+1) u5d (.clk(clk), .ce(ce), .a(MUL_LATENCY-5), .d(xc4), .q(xc5));
always @(posedge clk)
 
        if (ce) ex5 <= ex4;
 
always @(posedge clk)
 
        if (ce) xc5 <= xc4;
 
 
 
delay4 u2a (.clk(clk), .ce(ce), .i(aInf1), .o(aInf5) );
vtdl u2a (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(aInf1), .q(aInf5) );
delay4 u2b (.clk(clk), .ce(ce), .i(bInf1), .o(bInf5) );
vtdl u2b (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(bInf1), .q(bInf5) );
 
 
// determine when a NaN is output
// determine when a NaN is output
wire [MSB:0] a5,b5;
wire [MSB:0] a5,b5;
delay4 u5 (.clk(clk), .ce(ce), .i((aInf1&bz1)|(bInf1&az1)), .o(qNaNOut5) );
vtdl u5 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d((aInf1&bz1)|(bInf1&az1)), .q(qNaNOut5) );
delay4 u14 (.clk(clk), .ce(ce), .i(aNan1), .o(aNan5) );
vtdl u14 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(aNan1), .q(aNan5) );
delay4 u15 (.clk(clk), .ce(ce), .i(bNan1), .o(bNan5) );
vtdl u15 (.clk(clk), .ce(ce), .a(MUL_LATENCY-2), .d(bNan1), .q(bNan5) );
delay5 #(MSB+1) u16 (.clk(clk), .ce(ce), .i(a), .o(a5) );
vtdl #(MSB+1) u16 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(a), .q(a5) );
delay5 #(MSB+1) u17 (.clk(clk), .ce(ce), .i(b), .o(b5) );
vtdl #(MSB+1) u17 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(b), .q(b5) );
 
 
// -----------------------------------------------------------
// -----------------------------------------------------------
// Clock #6
// Clock #6
// - figure multiplier mantissa output
// - figure multiplier mantissa output
// - figure multiplier exponent output
// - figure multiplier exponent output
Line 411... Line 212...
 
 
reg [FX:0] mo6;
reg [FX:0] mo6;
reg [EMSB+2:0] ex6;
reg [EMSB+2:0] ex6;
reg [EMSB:0] xc6;
reg [EMSB:0] xc6;
wire [FMSB+1:0] fractc6;
wire [FMSB+1:0] fractc6;
vtdl #(FMSB+2) u61 (.clk(clk), .ce(ce), .a(4'd4), .d(fractc1), .q(fractc6) );
wire under6;
 
vtdl #(FMSB+2) u61 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(fractc1), .q(fractc6) );
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
delay1 u62 (.clk(clk), .ce(ce), .i(under5), .o(under6));
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce) xc6 <= xc5;
        if (ce) xc6 <= xc5;
 
 
Line 426... Line 228...
    6'b01????:  mo6 <= {1'b1,1'b1,b5[FMSB-1:0],{FMSB+1{1'b0}}};
    6'b01????:  mo6 <= {1'b1,1'b1,b5[FMSB-1:0],{FMSB+1{1'b0}}};
                6'b001???:      mo6 <= {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
                6'b001???:      mo6 <= {1'b1,qNaN|3'd4,{FMSB+1{1'b0}}}; // multiply inf * zero
                6'b0001??:      mo6 <= 0;        // mul inf's
                6'b0001??:      mo6 <= 0;        // mul inf's
                6'b00001?:      mo6 <= 0;        // mul inf's
                6'b00001?:      mo6 <= 0;        // mul inf's
                6'b000001:      mo6 <= 0;        // mul overflow
                6'b000001:      mo6 <= 0;        // mul overflow
                default:        mo6 <= fract5;
                default:        mo6 <= fract17;
                endcase
                endcase
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce)
        if (ce)
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
                casez({qNaNOut5|aNan5|bNan5,aInf5,bInf5,over5,under5})
Line 460... Line 262...
        if (ce) xeq7 <= (ex6=={2'b0,xc6});
        if (ce) xeq7 <= (ex6=={2'b0,xc6});
always @(posedge clk)
always @(posedge clk)
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
        if (ce) ma_gt_mc7 <= mo6 > {fractc6,{FMSB+1{1'b0}}};
always @(posedge clk)
always @(posedge clk)
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
        if (ce) meq7 <= mo6 == {fractc6,{FMSB+1{1'b0}}};
vtdl #(1) u71 (.clk(clk), .ce(ce), .a(4'd5), .d(az1), .q(az7));
vtdl #(1,32) u71 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(az1), .q(az7));
vtdl #(1) u72 (.clk(clk), .ce(ce), .a(4'd5), .d(bz1), .q(bz7));
vtdl #(1,32) u72 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(bz1), .q(bz7));
vtdl #(1) u73 (.clk(clk), .ce(ce), .a(4'd5), .d(cz1), .q(cz7));
vtdl #(1,32) u73 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(cz1), .q(cz7));
vtdl #(1) u74 (.clk(clk), .ce(ce), .a(4'd4), .d(realOp2), .q(realOp7));
vtdl #(1,32) u74 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(realOp2), .q(realOp7));
 
 
// -----------------------------------------------------------
// -----------------------------------------------------------
// Clock #8
// Clock #8
// - prep for addition, determine greater operand
// - prep for addition, determine greater operand
// - determine if result will be zero
// - determine if result will be zero
Line 483... Line 285...
wire op8;
wire op8;
wire sa8, sc8;
wire sa8, sc8;
 
 
delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
delay2 #(EMSB+3) u81 (.clk(clk), .ce(ce), .i(ex6), .o(ex8));
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
delay2 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xc6), .o(xc8));
vtdl #(1) u83 (.clk(clk), .ce(ce), .a(4'd5), .d(xcInf2), .q(xcInf8));
vtdl #(1,32) u83 (.clk(clk), .ce(ce), .a(MUL_LATENCY-1), .d(xcInf2), .q(xcInf8));
vtdl #(3) u84 (.clk(clk), .ce(ce), .a(4'd7), .d(rm), .q(rm8));
vtdl #(3,32) u84 (.clk(clk), .ce(ce), .a(MUL_LATENCY+1), .d(rm), .q(rm8));
vtdl #(1) u85 (.clk(clk), .ce(ce), .a(4'd6), .d(op1), .q(op8));
vtdl #(1,32) u85 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(op1), .q(op8));
vtdl #(1) u86 (.clk(clk), .ce(ce), .a(4'd6), .d(sa1 ^ sb1), .q(sa8));
vtdl #(1,32) u86 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(sa1 ^ sb1), .q(sa8));
vtdl #(1) u87 (.clk(clk), .ce(ce), .a(4'd6), .d(sc1), .q(sc8));
vtdl #(1,32) u87 (.clk(clk), .ce(ce), .a(MUL_LATENCY), .d(sc1), .q(sc8));
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
        if (ce) ex_gt_xc8 <= ex_gt_xc7;
always @(posedge clk)
always @(posedge clk)
        if (ce)
        if (ce)
Line 615... Line 417...
wire [FX:0] mfs12;
wire [FX:0] mfs12;
wire [7:0] xdif12;
wire [7:0] xdif12;
 
 
generate
generate
begin
begin
if (FPWID+`EXTRA_BITS==128)
if (FPWID==128)
    redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
    redor128 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==96)
else if (FPWID==80)
    redor96 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
 
else if (FPWID+`EXTRA_BITS==84)
 
    redor84 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
 
else if (FPWID+`EXTRA_BITS==80)
 
    redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
    redor80 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==64)
else if (FPWID==64)
    redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
    redor64 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
else if (FPWID+`EXTRA_BITS==32)
else if (FPWID==32)
    redor32 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
    redor32 u121 (.a(xdif11), .b({mfs,2'b0}), .o(sticky) );
end
end
endgenerate
endgenerate
 
 
// register inputs to shifter and shift
// register inputs to shifter and shift
Line 747... Line 545...
 
 
 
 
// Multiplier with normalization and rounding.
// Multiplier with normalization and rounding.
 
 
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, zero, overflow, underflow, inexact);
module fpFMAnr(clk, ce, op, rm, a, b, c, o, inf, zero, overflow, underflow, inexact);
parameter FPWID=64;
parameter FPWID=128;
`include "fpSize.sv"
`include "fpSize.sv"
 
 
input clk;
input clk;
input ce;
input ce;
input op;
input op;

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