| Line 48... |
Line 48... |
output [MSB+3:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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output [MSB+3:0] o; // normalized output + guard, sticky and round bits, + 1 whole digit
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input under_i;
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input under_i;
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output under_o;
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output under_o;
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output inexact_o;
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output inexact_o;
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integer n;
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// No Clock required
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// No Clock required
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo0;
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reg [EMSB:0] xo0;
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reg so0;
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reg so0;
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| Line 218... |
Line 218... |
always @(posedge clk)
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always @(posedge clk)
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1; // xo2 is negative !
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if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1; // xo2 is negative !
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #7
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// Clock edge #7
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// - fogure exponent
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// - figure exponent
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// - shift mantissa
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// - shift mantissa
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// - figure sticky bit
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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reg [EMSB:0] xo7;
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reg [EMSB:0] xo7;
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wire rightOrLeft7;
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wire rightOrLeft7;
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reg [FMSB+4:0] mo7l, mo7r;
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reg [FMSB+4:0] mo7l, mo7r;
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reg St6,St7;
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delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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xo7 <= zeroMan6 ? xo6 :
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xo7 <= zeroMan6 ? xo6 :
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| Line 239... |
Line 241... |
always @(posedge clk)
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always @(posedge clk)
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if (ce) mo7r <= mo6 >> rshiftAmt6;
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if (ce) mo7r <= mo6 >> rshiftAmt6;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mo7l <= mo6 << lshiftAmt6;
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if (ce) mo7l <= mo6 << lshiftAmt6;
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// The sticky bit is set if the bits shifted out on a right shift are set.
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always @*
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begin
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St6 = 1'b0;
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for (n = 0; n < FMSB+5; n = n + 1)
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if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
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end
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always @(posedge clk)
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if (ce) St7 <= St6;
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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// Clock edge #8
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// Clock edge #8
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// - select mantissa
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// - select mantissa
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// ----------------------------------------------------------------------------
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// ----------------------------------------------------------------------------
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| Line 254... |
Line 265... |
delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
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delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
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vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
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delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) mo <= rightOrLeft7 ? mo7r : mo7l;
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if (ce) mo <= rightOrLeft7 ? mo7r|{St7,1'b0} : mo7l;
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assign o = {so,xo,mo[FMSB+4:1]};
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assign o = {so,xo,mo[FMSB+4:1]};
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endmodule
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endmodule
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