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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpNormalize.sv] - Diff between revs 48 and 49

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Rev 48 Rev 49
Line 48... Line 48...
output [MSB+3:0] o;             // normalized output + guard, sticky and round bits, + 1 whole digit
output [MSB+3:0] o;             // normalized output + guard, sticky and round bits, + 1 whole digit
input under_i;
input under_i;
output under_o;
output under_o;
output inexact_o;
output inexact_o;
 
 
 
integer n;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// No Clock required
// No Clock required
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
reg [EMSB:0] xo0;
reg [EMSB:0] xo0;
reg so0;
reg so0;
Line 218... Line 218...
always @(posedge clk)
always @(posedge clk)
        if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1;    // xo2 is negative !
        if (ce) rshiftAmt6 <= xInf5 ? 1'd0 : $signed(xo5) > 1'd0 ? 1'd0 : ~xo5+2'd1;    // xo2 is negative !
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Clock edge #7
// Clock edge #7
// - fogure exponent
// - figure exponent
// - shift mantissa
// - shift mantissa
 
// - figure sticky bit
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
reg [EMSB:0] xo7;
reg [EMSB:0] xo7;
wire rightOrLeft7;
wire rightOrLeft7;
reg [FMSB+4:0] mo7l, mo7r;
reg [FMSB+4:0] mo7l, mo7r;
 
reg St6,St7;
delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
delay1 u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
 
 
always @(posedge clk)
always @(posedge clk)
if (ce)
if (ce)
        xo7 <= zeroMan6 ? xo6 :
        xo7 <= zeroMan6 ? xo6 :
Line 239... Line 241...
always @(posedge clk)
always @(posedge clk)
        if (ce) mo7r <= mo6 >> rshiftAmt6;
        if (ce) mo7r <= mo6 >> rshiftAmt6;
always @(posedge clk)
always @(posedge clk)
        if (ce) mo7l <= mo6 << lshiftAmt6;
        if (ce) mo7l <= mo6 << lshiftAmt6;
 
 
 
// The sticky bit is set if the bits shifted out on a right shift are set.
 
always @*
 
begin
 
  St6 = 1'b0;
 
  for (n = 0; n < FMSB+5; n = n + 1)
 
    if (n <= rshiftAmt6 + 1) St6 = St6|mo6[n];
 
end
 
always @(posedge clk)
 
  if (ce) St7 <= St6;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Clock edge #8
// Clock edge #8
// - select mantissa
// - select mantissa
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
Line 254... Line 265...
delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
delay1 #(EMSB+1) u82 (.clk(clk), .ce(ce), .i(xo7), .o(xo));
vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
vtdl u83 (.clk(clk), .ce(ce), .a(4'd3), .d(inexact4), .q(inexact_o));
delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
delay1 u84 (.clk(clk), .ce(ce), .i(rightOrLeft7), .o(under_o));
 
 
always @(posedge clk)
always @(posedge clk)
        if (ce) mo <= rightOrLeft7 ? mo7r : mo7l;
        if (ce) mo <= rightOrLeft7 ? mo7r|{St7,1'b0} : mo7l;
 
 
assign o = {so,xo,mo[FMSB+4:1]};
assign o = {so,xo,mo[FMSB+4:1]};
 
 
endmodule
endmodule
 
 

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