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Line 163... |
delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
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delay3 #(1) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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delay3 #(1) u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
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generate
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generate
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begin
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begin
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if (FPWID+`EXTRA_BITS <= 32) begin
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if (FPWID <= 32) begin
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
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cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
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assign leadingZeros5[7:6] = 2'b00;
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assign leadingZeros5[7:6] = 2'b00;
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end
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end
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else if (FPWID+`EXTRA_BITS<=64) begin
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else if (FPWID<=64) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
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cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID+`EXTRA_BITS<=80) begin
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else if (FPWID<=80) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID+`EXTRA_BITS<=84) begin
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else if (FPWID<=84) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID+`EXTRA_BITS<=96) begin
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else if (FPWID<=96) begin
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assign leadingZeros5[7] = 1'b0;
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assign leadingZeros5[7] = 1'b0;
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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else if (FPWID+`EXTRA_BITS<=128)
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else if (FPWID<=128)
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
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end
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end
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endgenerate
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endgenerate
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