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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [fpNormalize.v] - Diff between revs 29 and 32

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Rev 29 Rev 32
Line 163... Line 163...
delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
delay2 #(EMSB+1) u51 (.clk(clk), .ce(ce), .i(xo3), .o(xo5));
delay3 #(1)      u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
delay3 #(1)      u52 (.clk(clk), .ce(ce), .i(xInf2c), .o(xInf5) );
 
 
generate
generate
begin
begin
if (FPWID+`EXTRA_BITS <= 32) begin
if (FPWID <= 32) begin
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
cntlz32Reg clz0 (.clk(clk), .ce(ce), .i({mo4,5'b0}), .o(leadingZeros5) );
assign leadingZeros5[7:6] = 2'b00;
assign leadingZeros5[7:6] = 2'b00;
end
end
else if (FPWID+`EXTRA_BITS<=64) begin
else if (FPWID<=64) begin
assign leadingZeros5[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
cntlz64Reg clz0 (.clk(clk), .ce(ce), .i({mo4,8'h0}), .o(leadingZeros5) );
end
end
else if (FPWID+`EXTRA_BITS<=80) begin
else if (FPWID<=80) begin
assign leadingZeros5[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
cntlz80Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
else if (FPWID+`EXTRA_BITS<=84) begin
else if (FPWID<=84) begin
assign leadingZeros5[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,24'b0}), .o(leadingZeros5) );
end
end
else if (FPWID+`EXTRA_BITS<=96) begin
else if (FPWID<=96) begin
assign leadingZeros5[7] = 1'b0;
assign leadingZeros5[7] = 1'b0;
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
cntlz96Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
else if (FPWID+`EXTRA_BITS<=128)
else if (FPWID<=128)
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
cntlz128Reg clz0 (.clk(clk), .ce(ce), .i({mo4,12'b0}), .o(leadingZeros5) );
end
end
endgenerate
endgenerate
 
 
 
 

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