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// - floating point rounding unit
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// - floating point rounding unit
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// BSD 3-Clause License
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// it under the terms of the GNU Lesser General Public License as published
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// Redistribution and use in source and binary forms, with or without
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// by the Free Software Foundation, either version 3 of the License, or
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// modification, are permitted provided that the following conditions are met:
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// 1. Redistributions of source code must retain the above copyright notice, this
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// along with this program. If not, see .
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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import fp::*;
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import fp::*;
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`ifdef MIN_LATENCY
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`define PIPE_ADV *
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`else
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`define PIPE_ADV (posedge clk)
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`endif
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module fpRound(clk, ce, rm, i, o);
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module fpRound(clk, ce, rm, i, o);
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input clk;
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input clk;
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input ce;
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input ce;
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input [2:0] rm; // rounding mode
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input [2:0] rm; // rounding mode
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input [MSB+3:0] i; // intermediate format input
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input [MSB+3:0] i; // intermediate format input
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| Line 44... |
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reg [FMSB+3:0] mo1;
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reg [FMSB+3:0] mo1;
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wire xInf = &i[MSB+2:FMSB+4];
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wire xInf = &i[MSB+2:FMSB+4];
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wire so0 = i[MSB+3];
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wire so0 = i[MSB+3];
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assign o = {so,xo,mo};
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assign o = {so,xo,mo};
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wire l = i[3];
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wire g = i[2]; // guard bit: always the same bit for all operations
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wire g = i[2]; // guard bit: always the same bit for all operations
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wire r = i[1]; // rounding bit
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wire r = i[1]; // rounding bit
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wire s = i[0]; // sticky bit
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wire s = i[0]; // sticky bit
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reg rnd;
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reg rnd;
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Clock #1
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// Clock #1
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// - determine round amount (add 1 or 0)
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// - determine round amount (add 1 or 0)
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//------------------------------------------------------------
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//------------------------------------------------------------
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) xo1 <= i[MSB+2:FMSB+4];
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if (ce) xo1 <= i[MSB+2:FMSB+4];
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) mo1 <= i[FMSB+3:0];
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if (ce) mo1 <= i[FMSB+3:0];
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wire tie = g & ~(r|s);
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// Compute the round bit
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// Compute the round bit
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// Infinities and NaNs are not rounded!
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// Infinities and NaNs are not rounded!
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce)
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if (ce)
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casez ({xInf,rm})
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casez ({xInf,rm})
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4'b0000: rnd <= (g & r) | (r & s); // round to nearest even
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4'b0000: rnd <= (g & (r|s)) | (l & tie); // round to nearest ties to even
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4'b0001: rnd <= 1'd0; // round to zero (truncate)
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4'b0001: rnd <= 1'd0; // round to zero (truncate)
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4'b0010: rnd <= (r | s) & !so0; // round towards +infinity
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4'b0010: rnd <= g & !so0; // round towards +infinity
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4'b0011: rnd <= (r | s) & so0; // round towards -infinity
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4'b0011: rnd <= g & so0; // round towards -infinity
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4'b0100: rnd <= (r | s); // round to nearest away from zero
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4'b0100: rnd <= (g & (r|s)) | tie; // round to nearest ties away from zero
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4'b1???: rnd <= 1'd0; // no rounding if exponent indicates infinite or NaN
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4'b1???: rnd <= 1'd0; // no rounding if exponent indicates infinite or NaN
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default: rnd <= 0;
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default: rnd <= 0;
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endcase
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endcase
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//------------------------------------------------------------
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//------------------------------------------------------------
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reg [MSB:0] rounded2;
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reg [MSB:0] rounded2;
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reg carry2;
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reg carry2;
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reg rnd2;
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reg rnd2;
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reg dn2;
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reg dn2;
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wire [EMSB:0] xo2;
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wire [EMSB:0] xo2;
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wire [MSB:0] rounded1 = {xo1,mo1[FMSB+3:2]} + rnd;
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wire [MSB:0] rounded1 = {xo1,mo1[FMSB+3:3],1'b0} + {rnd,1'b0}; // Add onto LSB, GRS=0
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) rounded2 <= rounded1;
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if (ce) rounded2 <= rounded1;
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) carry2 <= mo1[FMSB+3] & !rounded1[FMSB+1];
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if (ce) carry2 <= mo1[FMSB+3] & !rounded1[FMSB+1];
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) rnd2 <= rnd;
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if (ce) rnd2 <= rnd;
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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`else
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always @(posedge clk)
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`endif
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if (ce) dn2 <= !(|xo1);
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if (ce) dn2 <= !(|xo1);
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assign xo2 = rounded2[MSB:FMSB+2];
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assign xo2 = rounded2[MSB:FMSB+2];
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Clock #3
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// Clock #3
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`else
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`else
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delay3 #(1) u21 (.clk(clk), .ce(ce), .i(i[MSB+3]), .o(so));
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delay3 #(1) u21 (.clk(clk), .ce(ce), .i(i[MSB+3]), .o(so));
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delay1 #(EMSB+1) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo));
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delay1 #(EMSB+1) u22 (.clk(clk), .ce(ce), .i(xo2), .o(xo));
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`endif
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`endif
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`ifdef MIN_LATENCY
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always @`PIPE_ADV
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always @*
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if (ce)
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`else
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always @(posedge clk)
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`endif
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casez({rnd2,&xo2,carry2,dn2})
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casez({rnd2,&xo2,carry2,dn2})
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4'b0??0: mo <= mo1[FMSB+2:2]; // not rounding, not denormalized, => hide MSB
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4'b0??0: mo <= mo1[FMSB+2:2]; // not rounding, not denormalized, => hide MSB
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4'b0??1: mo <= mo1[FMSB+3:3]; // not rounding, denormalized
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4'b0??1: mo <= mo1[FMSB+3:3]; // not rounding, denormalized
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4'b1000: mo <= rounded2[FMSB :0]; // exponent didn't change, number was normalized, => hide MSB,
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4'b1000: mo <= rounded2[FMSB :0]; // exponent didn't change, number was normalized, => hide MSB,
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4'b1001: mo <= rounded2[FMSB+1:1]; // exponent didn't change, but number was denormalized, => retain MSB
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4'b1001: mo <= rounded2[FMSB+1:1]; // exponent didn't change, but number was denormalized, => retain MSB
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4'b1011: mo <= rounded2[FMSB+1:1]; // exponent incremented (new MSB generated), number was denormalized, number became normalized, => hide 'extra (FMSB+2)' MSB
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4'b1011: mo <= rounded2[FMSB+1:1]; // exponent incremented (new MSB generated), number was denormalized, number became normalized, => hide 'extra (FMSB+2)' MSB
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4'b11??: mo <= 1'd0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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4'b11??: mo <= 1'd0; // number became infinite, no need to check carry etc., rnd would be zero if input was NaN or infinite
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endcase
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endcase
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endmodule
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endmodule
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// Round and register the output
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/*
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module fpRoundReg(clk, ce, rm, i, o);
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parameter WID = 128;
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`include "fpSize.sv"
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input clk;
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input ce;
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input [2:0] rm; // rounding mode
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input [MSB+3:0] i; // expanded format input
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output reg [WID-1:0] o; // rounded output
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wire [WID-1:0] o1;
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fpRound #(WID) u1 (.rm(rm), .i(i), .o(o1) );
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always @(posedge clk)
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if (ce)
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o <= o1;
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endmodule
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*/
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No newline at end of file
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No newline at end of file
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