URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
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Rev 34 |
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpdivr16.v
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// fpdivr16.v
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b3 = b <= {r3,q[WID*2-4]};
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b3 = b <= {r3,q[WID*2-4]};
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always @*
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always @*
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r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
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r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
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reg [2:0] state = 0;
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reg [2:0] state = 0;
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always @(posedge clk)
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begin
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if (ld) state <= 3'd1;
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case(state)
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3'd0: ;
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3'd1: if (cnt[8]) state <= 3'd2;
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3'd2: state <= 3'd0;
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default: state <= 3'd0;
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endcase
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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done <= 1'b0;
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done <= 1'b0;
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case(state)
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case(state)
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Line 108... |
gotnz <= 3'd1;
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gotnz <= 3'd1;
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end
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end
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rxx <= r4;
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rxx <= r4;
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cnt <= cnt - 3'd1;
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cnt <= cnt - 3'd1;
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end
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end
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else
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state <= 3'd2;
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3'd2:
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3'd2:
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begin
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begin
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r <= r4;
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r <= r4;
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done <= 1'b1;
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done <= 1'b1;
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state <= 1'd0;
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end
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end
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default: state <= 1'd0;
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default: ;
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endcase
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endcase
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if (ld) begin
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if (ld) begin
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lzcnt <= 0;
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lzcnt <= 0;
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gotnz <= 1'b0;
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gotnz <= 1'b0;
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cnt <= {1'b0,maxcnt};
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cnt <= {1'b0,maxcnt};
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q <= {(a << REM),{WID{1'b0}}};
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q <= {(a << REM),{WID{1'b0}}};
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rxx <= {WID{1'b0}};
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rxx <= {WID{1'b0}};
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state <= 3'd1;
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end
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end
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end
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end
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endmodule
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endmodule
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