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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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module fpdivr16(clk, ld, a, b, q, r, done, lzcnt);
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module fpdivr16(clk, ld, a, b, q, r, done, lzcnt);
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parameter FPWID1 = 112;
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parameter WID1 = 112;
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localparam REM = FPWID1 % 4;
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localparam REM = WID1 % 4;
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localparam FPWID = ((FPWID1*4)+3)/4;
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localparam WID = ((WID1*4)+3)/4;
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localparam DMSB = FPWID-1;
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localparam DMSB = WID-1;
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input clk;
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input clk;
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input ld;
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input ld;
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input [FPWID-1:0] a;
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input [WID-1:0] a;
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input [FPWID-1:0] b;
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input [WID-1:0] b;
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output reg [FPWID*2-1:0] q = 1'd0;
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output reg [WID*2-1:0] q = 1'd0;
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output reg [FPWID-1:0] r = 1'd0;
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output reg [WID-1:0] r = 1'd0;
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output reg done = 1'd0;
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output reg done = 1'd0;
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output reg [7:0] lzcnt = 1'd0;
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output reg [7:0] lzcnt = 1'd0;
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initial begin
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initial begin
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if (FPWID % 4) begin
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if (WID % 4) begin
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$display("fpdvir16: FPWIDth must be a multiple of four.");
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$display("fpdvir16: Width must be a multiple of four.");
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$finish;
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$finish;
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end
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end
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end
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end
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wire [7:0] maxcnt;
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wire [7:0] maxcnt;
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reg [DMSB+1:0] ri = 1'd0;
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reg [DMSB+1:0] ri = 1'd0;
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reg b0 = 1'd0,b1 = 1'd0,b2 = 1'd0,b3 = 1'd0;
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reg b0 = 1'd0,b1 = 1'd0,b2 = 1'd0,b3 = 1'd0;
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reg [DMSB+1:0] r1 = 1'd0,r2 = 1'd0,r3 = 1'd0,r4 = 1'd0;
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reg [DMSB+1:0] r1 = 1'd0,r2 = 1'd0,r3 = 1'd0,r4 = 1'd0;
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reg gotnz = 0;
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reg gotnz = 0;
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assign maxcnt = FPWID*2/4-1;
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assign maxcnt = WID*2/4-1;
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always @*
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always @*
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b0 = b <= {rxx,q[FPWID*2-1]};
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b0 = b <= {rxx,q[WID*2-1]};
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always @*
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always @*
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r1 = b0 ? {rxx,q[FPWID*2-1]} - b : {rxx,q[FPWID*2-1]};
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r1 = b0 ? {rxx,q[WID*2-1]} - b : {rxx,q[WID*2-1]};
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always @*
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always @*
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b1 = b <= {r1,q[FPWID*2-2]};
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b1 = b <= {r1,q[WID*2-2]};
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always @*
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always @*
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r2 = b1 ? {r1,q[FPWID*2-2]} - b : {r1,q[FPWID*2-2]};
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r2 = b1 ? {r1,q[WID*2-2]} - b : {r1,q[WID*2-2]};
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always @*
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always @*
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b2 = b <= {r2,q[FPWID*2-3]};
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b2 = b <= {r2,q[WID*2-3]};
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always @*
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always @*
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r3 = b2 ? {r2,q[FPWID*2-3]} - b : {r2,q[FPWID*2-3]};
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r3 = b2 ? {r2,q[WID*2-3]} - b : {r2,q[WID*2-3]};
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always @*
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always @*
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b3 = b <= {r3,q[FPWID*2-4]};
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b3 = b <= {r3,q[WID*2-4]};
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always @*
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always @*
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r4 = b3 ? {r3,q[FPWID*2-4]} - b : {r3,q[FPWID*2-4]};
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r4 = b3 ? {r3,q[WID*2-4]} - b : {r3,q[WID*2-4]};
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reg [2:0] state = 0;
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reg [2:0] state = 0;
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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done <= 1'b0;
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done <= 1'b0;
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case(state)
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case(state)
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3'd0:
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3'd0: ;
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if (ld) begin
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lzcnt <= 0;
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gotnz <= 0;
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cnt <= maxcnt;
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q <= {(a << REM),{FPWID{1'b0}}};
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rxx <= {FPWID{1'b0}};
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state <= 1;
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end
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3'd1:
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3'd1:
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if (!cnt[8]) begin
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if (!cnt[8]) begin
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q[FPWID*2-1:4] <= q[FPWID*2-5:0];
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q[WID*2-1:4] <= q[WID*2-5:0];
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q[3] <= b0;
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q[3] <= b0;
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q[2] <= b1;
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q[2] <= b1;
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q[1] <= b2;
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q[1] <= b2;
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q[0] <= b3;
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q[0] <= b3;
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if (!gotnz)
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if (!gotnz)
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done <= 1'b1;
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done <= 1'b1;
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state <= 1'd0;
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state <= 1'd0;
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end
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end
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default: state <= 1'd0;
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default: state <= 1'd0;
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endcase
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endcase
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if (ld) begin
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lzcnt <= 0;
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gotnz <= 1'b0;
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cnt <= {1'b0,maxcnt};
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q <= {(a << REM),{WID{1'b0}}};
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rxx <= {WID{1'b0}};
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state <= 3'd1;
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end
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end
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end
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endmodule
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endmodule
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