| Line 1... |
Line 1... |
|
`timescale 1ns / 1ps
|
// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2010-2019 Robert Finch, Waterloo
|
// \\__/ o\ (C) 2010-2019 Robert Finch, Waterloo
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@finitron.ca
|
// \/_// robfinch<remove>@finitron.ca
|
| Line 7... |
Line 8... |
//
|
//
|
// isqrt.v
|
// isqrt.v
|
// - integer square root
|
// - integer square root
|
// - uses the standard long form calc.
|
// - uses the standard long form calc.
|
// - geared towards use in an floating point unit
|
// - geared towards use in an floating point unit
|
// - calculates to FPWID fractional precision (double FPWIDth output)
|
// - calculates to WID fractional precision (double width output)
|
//
|
//
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
// it under the terms of the GNU Lesser General Public License as published
|
// it under the terms of the GNU Lesser General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or
|
// by the Free Software Foundation, either version 3 of the License, or
|
| Line 26... |
Line 27... |
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
|
|
module isqrt(rst, clk, ce, ld, a, o, done);
|
module isqrt(rst, clk, ce, ld, a, o, done);
|
parameter FPWID = 32;
|
parameter WID = 32;
|
localparam MSB = FPWID-1;
|
localparam MSB = WID-1;
|
parameter IDLE=3'd0;
|
parameter IDLE=3'd0;
|
parameter CALC=3'd1;
|
parameter CALC=3'd1;
|
parameter DONE=3'd2;
|
parameter DONE=3'd2;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
input ce;
|
input ce;
|
input ld;
|
input ld;
|
input [MSB:0] a;
|
input [MSB:0] a;
|
output [FPWID*2-1:0] o;
|
output [WID*2-1:0] o;
|
output done;
|
output done;
|
|
|
reg [2:0] state;
|
reg [2:0] state;
|
reg [FPWID*2:0] root;
|
reg [WID*2:0] root;
|
wire [FPWID*2-1:0] testDiv;
|
wire [WID*2-1:0] testDiv;
|
reg [FPWID*2-1:0] remLo;
|
reg [WID*2-1:0] remLo;
|
reg [FPWID*2-1:0] remHi;
|
reg [WID*2-1:0] remHi;
|
|
|
wire cnt_done;
|
wire cnt_done;
|
assign testDiv = {root[FPWID*2-2:0],1'b1};
|
assign testDiv = {root[WID*2-2:0],1'b1};
|
wire [FPWID*2-1:0] remHiShift = {remHi[FPWID*2-3:0],remLo[FPWID*2-1:FPWID*2-2]};
|
wire [WID*2-1:0] remHiShift = {remHi[WID*2-3:0],remLo[WID*2-1:WID*2-2]};
|
wire doesGoInto = remHiShift >= testDiv;
|
wire doesGoInto = remHiShift >= testDiv;
|
assign o = root[FPWID*2:1];
|
assign o = root[WID*2:1];
|
|
|
// Iteration counter
|
// Iteration counter
|
reg [7:0] cnt;
|
reg [7:0] cnt;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst) begin
|
if (rst) begin
|
cnt <= FPWID*2;
|
cnt <= WID*2;
|
remLo <= {FPWID*2{1'b0}};
|
remLo <= {WID*2{1'b0}};
|
remHi <= {FPWID*2{1'b0}};
|
remHi <= {WID*2{1'b0}};
|
root <= {FPWID*2+1{1'b0}};
|
root <= {WID*2+1{1'b0}};
|
state <= IDLE;
|
state <= IDLE;
|
end
|
end
|
else if (ce) begin
|
else
|
|
begin
|
|
if (ce) begin
|
if (!cnt_done)
|
if (!cnt_done)
|
cnt <= cnt + 8'd1;
|
cnt <= cnt + 8'd1;
|
case(state)
|
case(state)
|
IDLE:
|
IDLE: ;
|
if (ld) begin
|
|
cnt <= 8'd0;
|
|
state <= CALC;
|
|
remLo <= {a,32'h0};
|
|
remHi <= {FPWID*2{1'b0}};
|
|
root <= {FPWID*2+1{1'b0}};
|
|
end
|
|
CALC:
|
CALC:
|
if (!cnt_done) begin
|
if (!cnt_done) begin
|
// Shift the remainder low
|
// Shift the remainder low
|
remLo <= {remLo[FPWID*2-3:0],2'd0};
|
remLo <= {remLo[WID*2-3:0],2'd0};
|
// Shift the remainder high
|
// Shift the remainder high
|
remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
|
remHi <= doesGoInto ? remHiShift - testDiv: remHiShift;
|
// Shift the root
|
// Shift the root
|
root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
|
root <= {root+doesGoInto,1'b0}; // root * 2 + 1/0
|
end
|
end
|
| Line 93... |
Line 89... |
begin
|
begin
|
cnt <= cnt + 8'd1;
|
cnt <= cnt + 8'd1;
|
if (cnt == 8'd6)
|
if (cnt == 8'd6)
|
state <= IDLE;
|
state <= IDLE;
|
end
|
end
|
|
default: state <= IDLE;
|
endcase
|
endcase
|
|
if (ld) begin
|
|
cnt <= 8'd0;
|
|
state <= CALC;
|
|
remLo <= {a,32'd0};
|
|
remHi <= {WID*2{1'b0}};
|
|
root <= {WID*2+1{1'b0}};
|
|
end
|
|
end
|
end
|
end
|
assign cnt_done = (cnt==FPWID);
|
assign cnt_done = (cnt==WID);
|
assign done = state==DONE;
|
assign done = state==DONE;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
