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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [mult128x128.sv] - Diff between revs 72 and 73

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Rev 72 Rev 73
Line 35... Line 35...
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// ============================================================================
// ============================================================================
 
 
//`define KARATSUBA     1
`define KARATSUBA       1
 
 
`ifdef KARATSUBA
`ifdef KARATSUBA
 
 
module mult128x128(clk, ce, a, b, o);
module mult128x128(clk, ce, a, b, o);
input clk;
input clk;
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input [127:0] b;
input [127:0] b;
output reg [255:0] o;
output reg [255:0] o;
 
 
reg [63:0] a2, b2;
reg [63:0] a2, b2;
reg [64:0] a1, b1;
reg [64:0] a1, b1;
reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4;
reg [127:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3;
 
reg [128:0] p4;
reg [128:0] z1; // extra bit for carry
reg [128:0] z1; // extra bit for carry
reg sgn2, sgn10;
reg sgn2, sgn10;
wire sgn9;
wire sgn9;
 
 
always @(posedge clk)
always @(posedge clk)
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always @(posedge clk)
always @(posedge clk)
  if (ce) z2c <= z2b;
  if (ce) z2c <= z2b;
always @(posedge clk)
always @(posedge clk)
  if (ce) z0c <= z0b;
  if (ce) z0c <= z0b;
always @(posedge clk)
always @(posedge clk)
        if (ce) z1 <= {{128{sgn10}},p4} + z2c + z0c;
        if (ce) z1 <= {{128{p4[128]}},p4} + z2c + z0c;
 
 
always @(posedge clk)
always @(posedge clk)
  if (ce) z2d <= z2c;
  if (ce) z2d <= z2c;
always @(posedge clk)
always @(posedge clk)
  if (ce) z0d <= z0c;
  if (ce) z0d <= z0c;

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