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[/] [ft816float/] [trunk/] [rtl/] [verilog2/] [mult32x32.sv] - Diff between revs 72 and 73

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Rev 72 Rev 73
Line 48... Line 48... 
input [31:0] b;
 
input [31:0] b;
 
output reg [63:0] o;
 
output reg [63:0] o;
 
 
 
 
 
reg [15:0] a2, b2;
 
reg [15:0] a2, b2;
 
reg [16:0] a1, b1;
 
reg [16:0] a1, b1;
 
reg [31:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3, p4;
 
reg [31:0] z0, z2, z0a, z2a, z0b, z2b, z0c, z2c, z0d, z2d, p3;
 
 
 
reg [32:0] p4;
 
reg [32:0] z1;  // extra bit for carry
 
reg [32:0] z1;  // extra bit for carry
 
reg sgn2, sgn3, sgn4;
 
reg sgn2, sgn3, sgn4;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) a1 <= a[15: 0] - a[31:16];  // x0-x1
 
        if (ce) a1 <= a[15: 0] - a[31:16];  // x0-x1
Line 107... Line 108... 
always @(posedge clk)
 
always @(posedge clk)
 
  if (ce) z2c <= z2b;
 
  if (ce) z2c <= z2b;
 
always @(posedge clk)
 
always @(posedge clk)
 
  if (ce) z0c <= z0b;
 
  if (ce) z0c <= z0b;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (ce) z1 <= {{32{sgn4}},p4} + z2c + z0c;
 
        if (ce) z1 <= {{32{p4[32]}},p4} + z2c + z0c;
 
 
 
 
 
always @(posedge clk)
 
always @(posedge clk)
 
  if (ce) z2d <= z2c;
 
  if (ce) z2d <= z2c;
 
always @(posedge clk)
 
always @(posedge clk)
 
  if (ce) z0d <= z0c;
 
  if (ce) z0d <= z0c;

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