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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// mult64x64.sv
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// mult64x64.sv
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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//`define KARATSUBA 1
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`ifdef KARATSUBA
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module mult64x64(clk, ce, a, b, o);
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module mult64x64(clk, ce, a, b, o);
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input clk;
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input clk;
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input ce;
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input ce;
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input [63:0] a;
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input [63:0] a;
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input [63:0] b;
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input [63:0] b;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) b2 <= b1[32] ? -b1 : b1;
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if (ce) b2 <= b1[32] ? -b1 : b1;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sgn2 <= a1[32]^b1[32];
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if (ce) sgn2 <= a1[32]^b1[32];
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delay #(.WID(1), .DEP(7)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
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ft_delay #(.WID(1), .DEP(7)) udl1 (.clk(clk), .ce(ce), .i(sgn2), .o(sgn9));
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always @(posedge clk)
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always @(posedge clk)
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if (ce) sgn10 <= sgn9;
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if (ce) sgn10 <= sgn9;
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// 6 cycle latency
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// 6 cycle latency
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mult32x32 u1 (
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mult32x32 u1 (
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if (ce) z0d <= z0c;
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if (ce) z0d <= z0c;
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always @(posedge clk)
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always @(posedge clk)
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if (ce) o <= {z2d,z0d} + {z1,32'd0};
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if (ce) o <= {z2d,z0d} + {z1,32'd0};
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endmodule
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endmodule
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`else
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// This version of the multiply has a parameterized pipeline depth and allows
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// the tools to perform the multiply. Relies on the ability of tools to retime.
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module mult64x64(clk, ce, a, b, o);
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parameter DEP = 11;
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input clk;
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input ce;
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input [63:0] a;
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input [63:0] b;
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output reg [127:0] o;
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reg [127:0] prod [0:DEP-1];
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reg [127:0] prd;
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integer n;
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always_ff @(posedge clk)
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if (ce) prd <= a * b;
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always_ff @(posedge clk)
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if (ce) prod[0] <= prd;
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always_ff @(posedge clk)
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for (n = 0; n < DEP - 1; n = n + 1)
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if (ce) prod[n+1] <= prod[n];
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always_ff @(posedge clk)
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if(ce) o <= prod[DEP-1];
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endmodule
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`endif
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