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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2019 Robert Finch, Waterloo
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// fpAddsub_tb.v
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// fpAddsub_tb.v
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// - floating point divider test bench
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// BSD 3-Clause License
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// it under the terms of the GNU Lesser General Public License as published
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// Redistribution and use in source and binary forms, with or without
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// by the Free Software Foundation, either version 3 of the License, or
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// modification, are permitted provided that the following conditions are met:
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// 1. Redistributions of source code must retain the above copyright notice, this
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// ============================================================================
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// ============================================================================
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module fpAddsub_tb();
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module fpAddsub_tb();
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reg rst;
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reg rst;
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reg clk;
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reg clk;
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reg [15:0] adr;
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reg [15:0] adr;
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reg [103:0] mem [0:38000];
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reg [63:0] a,b;
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reg [103:0] memo [0:38000];
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wire [63:0] o;
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reg [199:0] memd [0:38000];
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reg [199:0] memdo [0:38000];
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reg [391:0] memq [0:38000];
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reg [391:0] memqo [0:38000];
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reg [31:0] a,b,a6,b6;
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reg [63:0] ad, bd;
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reg [63:0] ad, bd;
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reg [127:0] aq, bq;
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reg [63:0] od;
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wire [127:0] oq;
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reg [3:0] rm;
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wire [31:0] a5,b5;
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wire [31:0] o;
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wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
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wire [63:0] od;
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wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
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reg [3:0] rm, op, rmq, opq, rmd, opd;
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wire [3:0] rm5;
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integer outfile;
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wire [3:0] op5;
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initial begin
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initial begin
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rst = 1'b0;
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rst = 1'b0;
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clk = 1'b0;
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clk = 1'b0;
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adr = 0;
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adr = 0;
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$readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvs.txt", mem);
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a = $urandom(1);
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$readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvd.txt", memd);
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b = 1;
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$readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvq.txt", memq);
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#20 rst = 1;
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#20 rst = 1;
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#50 rst = 0;
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#50 rst = 0;
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#10000000 $fclose(outfile);
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#10 $finish;
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end
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end
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always #5
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always #5
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clk = ~clk;
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clk = ~clk;
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reg [7:0] count;
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reg [7:0] count;
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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adr <= 0;
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adr <= 0;
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count <= 0;
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count <= 0;
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end
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end
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else
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else
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begin
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begin
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if (adr==0) begin
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outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/fpAddsub_tvo.txt", "wb");
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$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
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end
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count <= count + 1;
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count <= count + 1;
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if (count==49)
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if (count > 32)
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count <= 0;
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count <= 1'd1;
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if (count==2) begin
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if (count==2) begin
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a <= mem[adr][31: 0];
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a[31:0] <= $urandom();
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b <= mem[adr][63:32];
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b[31:0] <= $urandom();
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rm <= mem[adr][99:96];
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a[63:32] <= $urandom();
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op <= mem[adr][103:100];
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b[63:32] <= $urandom();
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ad <= memq[adr][63: 0];
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rm <= adr[14:12];
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bd <= memq[adr][127:64];
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//ad <= memd[adr][63: 0];
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rmd <= memq[adr][195:192];
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//bd <= memd[adr][127:64];
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opd <= memq[adr][199:196];
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end
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aq <= memq[adr][127: 0];
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if (count==31) begin
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bq <= memq[adr][255:128];
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if (adr[11]) begin
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rmq <= memq[adr][387:384];
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od = $realtobits($bitstoreal(a) - $bitstoreal(b));
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opq <= memq[adr][391:388];
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\t%h%c\n", "-",rm, a, b, o, od,od!=o ? "*":" ");
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end
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end
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if (count==48) begin
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else begin
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memo[adr] <= {op,rm,o,b,a};
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od = $realtobits($bitstoreal(a) + $bitstoreal(b));
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memdo[adr] <= {opd,rmd,od,bd,ad};
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$fwrite(outfile, "%c%h\t%h\t%h\t%h\t%h%c\n", "+",rm, a, b, o, od,od!=o ? "*":" ");
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memqo[adr] <= {opq,rmq,oq,bq,aq};
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if (adr==8192) begin
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$writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvso.txt", memo);
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$writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvdo.txt", memdo);
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$writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvqo.txt", memqo);
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$finish;
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end
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end
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adr <= adr + 1;
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adr <= adr + 1;
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end
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end
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end
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end
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fpAddsubnr #(32) u1 (clk, 1'b1, rm[2:0], op[0], a, b, o);
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//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
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fpAddsubnr #(64) u2 (clk, 1'b1, rmd[2:0], opd[0], ad, bd, od);
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fpAddsubnr u6 (
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fpAddsubnr #(128) u3 (clk, 1'b1, rmq[2:0], opq[0], aq, bq, oq);
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.clk(clk),
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.ce(1'b1),
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.op(adr[11]),
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.a(a),
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.b(b),
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.o(o),
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.rm(rm)
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);
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endmodule
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endmodule
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