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`timescale 1ns / 1ps
// ============================================================================
// ============================================================================
//        __
//        __
//   \\__/ o\    (C) 2019  Robert Finch, Waterloo
//   \\__/ o\    (C) 2006-2020  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//
//
//      fpAddsub_tb.v
//      fpAddsub_tb.v
 
//              - floating point divider test bench
//
//
// This source file is free software: you can redistribute it and/or modify 
// BSD 3-Clause License
// it under the terms of the GNU Lesser General Public License as published 
// Redistribution and use in source and binary forms, with or without
// by the Free Software Foundation, either version 3 of the License, or     
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//                                                                          
 
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
 
// GNU General Public License for more details.                             
 
//                                                                          
//                                                                          
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// 1. Redistributions of source code must retain the above copyright notice, this
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//    list of conditions and the following disclaimer.
 
//
 
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// ============================================================================
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module fpAddsub_tb();
module fpAddsub_tb();
reg rst;
reg rst;
reg clk;
reg clk;
reg [15:0] adr;
reg [15:0] adr;
reg [103:0] mem [0:38000];
reg [63:0] a,b;
reg [103:0] memo [0:38000];
wire [63:0] o;
reg [199:0] memd [0:38000];
 
reg [199:0] memdo [0:38000];
 
reg [391:0] memq [0:38000];
 
reg [391:0] memqo [0:38000];
 
reg [31:0] a,b,a6,b6;
 
reg [63:0] ad, bd;
reg [63:0] ad, bd;
reg [127:0] aq, bq;
reg [63:0] od;
wire [127:0] oq;
reg [3:0] rm;
wire [31:0] a5,b5;
 
wire [31:0] o;
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
wire [63:0] od;
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
reg [3:0] rm, op, rmq, opq, rmd, opd;
 
wire [3:0] rm5;
integer outfile;
wire [3:0] op5;
 
 
 
initial begin
initial begin
        rst = 1'b0;
        rst = 1'b0;
        clk = 1'b0;
        clk = 1'b0;
        adr = 0;
        adr = 0;
        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvs.txt", mem);
        a = $urandom(1);
        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvd.txt", memd);
        b = 1;
        $readmemh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvq.txt", memq);
 
        #20 rst = 1;
        #20 rst = 1;
        #50 rst = 0;
        #50 rst = 0;
 
        #10000000  $fclose(outfile);
 
        #10 $finish;
end
end
 
 
always #5
always #5
        clk = ~clk;
        clk = ~clk;
 
 
reg [7:0] count;
reg [7:0] count;
 
 
always @(posedge clk)
always @(posedge clk)
if (rst) begin
if (rst) begin
        adr <= 0;
        adr <= 0;
        count <= 0;
        count <= 0;
end
end
else
else
begin
begin
 
  if (adr==0) begin
 
    outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/fpu/test_bench/fpAddsub_tvo.txt", "wb");
 
    $fwrite(outfile, " rm ------- A ------  ------- B ------  ------ sum -----  -- SIM Sum --\n");
 
  end
        count <= count + 1;
        count <= count + 1;
        if (count==49)
        if (count > 32)
                count <= 0;
                count <= 1'd1;
        if (count==2) begin
        if (count==2) begin
                a <= mem[adr][31: 0];
                a[31:0] <= $urandom();
                b <= mem[adr][63:32];
                b[31:0] <= $urandom();
                rm <= mem[adr][99:96];
                a[63:32] <= $urandom();
                op <= mem[adr][103:100];
                b[63:32] <= $urandom();
                ad <= memq[adr][63: 0];
                rm <= adr[14:12];
                bd <= memq[adr][127:64];
                //ad <= memd[adr][63: 0];
                rmd <= memq[adr][195:192];
                //bd <= memd[adr][127:64];
                opd <= memq[adr][199:196];
        end
                aq <= memq[adr][127: 0];
        if (count==31) begin
                bq <= memq[adr][255:128];
                if (adr[11]) begin
                rmq <= memq[adr][387:384];
                  od = $realtobits($bitstoreal(a) - $bitstoreal(b));
                opq <= memq[adr][391:388];
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\t%h%c\n", "-",rm, a, b, o, od,od!=o ? "*":" ");
        end
          end
        if (count==48) begin
          else begin
                memo[adr] <= {op,rm,o,b,a};
                  od = $realtobits($bitstoreal(a) + $bitstoreal(b));
                memdo[adr] <= {opd,rmd,od,bd,ad};
                $fwrite(outfile, "%c%h\t%h\t%h\t%h\t%h%c\n", "+",rm, a, b, o, od,od!=o ? "*":" ");
                memqo[adr] <= {opq,rmq,oq,bq,aq};
 
                if (adr==8192) begin
 
                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvso.txt", memo);
 
                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvdo.txt", memdo);
 
                        $writememh("d:/cores6/nvio/v2/rtl/fpUnit/test_bench/fpAddsub_tvqo.txt", memqo);
 
                        $finish;
 
                end
                end
                adr <= adr + 1;
                adr <= adr + 1;
        end
        end
end
end
 
 
fpAddsubnr #(32) u1 (clk, 1'b1, rm[2:0], op[0], a, b, o);
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
fpAddsubnr #(64) u2 (clk, 1'b1, rmd[2:0], opd[0], ad, bd, od);
fpAddsubnr u6 (
fpAddsubnr #(128) u3 (clk, 1'b1, rmq[2:0], opq[0], aq, bq, oq);
  .clk(clk),
 
  .ce(1'b1),
 
  .op(adr[11]),
 
  .a(a),
 
  .b(b),
 
  .o(o),
 
  .rm(rm)
 
  );
 
 
endmodule
endmodule
 
 
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