URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [nios_ii_sram.1.0.xml] - Diff between revs 157 and 188

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Rev 157	Rev 188
Line 6...	Line 6...

`Altera`	`Altera`
`ip.hwp.cpu`	`ip.hwp.cpu`
`nios_ii_sram`	`nios_ii_sram`
`1.0`	`1.0`
`Nios2 SRAM subsystem`	`Nios2 subsystem using SRAM as a data and program memory.`
	`Includes HIBI_PE_DMA for hibi communication.`




`clk`	`clk`


Line 425...	Line 428...
`Shared_memory`	`Shared_memory`
`0x1000000`	`0x1000000`
`4K`	`4K`


`8`	`32`

`avalon_addr_space`	`avalon_addr_space`

`HIBI_PE_DMA`	`HIBI_PE_DMA`
`0x0`	`0x500`
`4`	`64`
`32`	`32`
`reserved`	`register`

	`RX_INITIALIZE`
	`Initializes the channel`
	`0`
	`0x0`
	`32`
	`false`
	`write-only`


	`CONTROL`
	`Control register`
	`0`
	`0x1`
	`32`
	`read-write`


	`IRQ_STATUS`
	`Read IRQ status and acknoledge interrupts`
	`0`
	`0x2`
	`32`
	`read-write`


	`TX_MEM_ADDR`
	`Address where data to be sent begins`
	`0`
	`0x3`
	`32`
	`write-only`


	`TX_WORDS`
	`How many words to send`
	`0`
	`0x4`
	`32`
	`read-only`


	`TX_COMM`
	`Hibi command to send the data with`
	`0`
	`0x5`
	`32`
	`write-only`


	`TX_HIBI_ADDR`
	`Hibi address to send the data`
	`0`
	`0x6`
	`32`
	`write-only`


	`RX_HIBI_DATA`
	`Current data on hibi rx interface`
	`0`
	`0x7`
	`32`
	`read-only`


	`RX_MEM_ADDR`
	`Address where channel n stores received data`
	`0`
	`0x8`
	`32`
	`read-write`


	`RX_WORDS`
	`How many words to receive for packet channel n or read`
	`acknowledge for stream channel n`
	`0`
	`0x9`
	`32`
	`read-write`


	`RX_HIBI_ADDR`
	`Hibi address for channel n to listen`
	`0`
	`0xA`
	`32`
	`read-write`



`JTAG_UART`	`JTAG_UART`
`0x4`	`0x100`
`4`	`4`
`32`	`32`
`reserved`	`reserved`


`TIMER`	`TIMER`
`0x8`	`0x300`
`4`	`4`
`32`	`32`
`reserved`	`reserved`


Line 458...	Line 551...
`32`	`32`
`memory`	`memory`


`SYSID`	`SYSID`
`0x10`	`0x200`
`4`	`4`
`32`	`32`
`reserved`	`reserved`


Line 483...	Line 576...




`hibi_mem_map`	`hibi_mem_map`

	`hibi_addr_block`
	`0x0`
	`32`
	`32`
	`reserved`

`32`	`32`




Line 774...	Line 874...
`hdl/onchip_memory_0.v`	`hdl/onchip_memory_0.v`
`verilogSource`	`verilogSource`
`false`	`false`



	`avalon_addr_space_header`
	`Contains header files generated for the component.`
	`generatedFiles`

	`headers/avalon_addr_space.h`
	`cSource`
	`cppSource`
	`true`
	`A header file generated by Kactus2.`
	`This file contains the register and memory addresses defined in the memory map(s)`





`nios2`	`nios2`

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[/] [funbase_ip_library/] [trunk/] [Altera/] [ip.hwp.cpu/] [nios_ii_sram/] [1.0/] [nios_ii_sram.1.0.xml] - Diff between revs 157 and 188