URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [board/] [altera_de2_board/] [1.0/] [altera_de2_board.design.1.0.xml] - Diff between revs 145 and 147

Rev 145	Rev 147
Line 1...	Line 1...






`TUT`	`TUT`
`board`	`board`
`altera_de2_board.design`	`altera_de2_board.design`
`1.0`	`1.0`


`dm_9000_eth_ctrl`	`SRAM_512KB`


















`clock_osc_50MHz`	`SDRAM_8MB`


















Line 59...	Line 59...





`SDRAM_8MB`	`clock_osc_50MHz`


















`SRAM_512KB`	`dm_9000_eth_ctrl`
















Line 128...	Line 128...





`push_buttons_0_button_17_to_cyclone_II_0_rst_n`	`cyclone_II_0_sdram_if_to_SDRAM_8MB_sdram_if`






`cyclone_II_0_DM9000A_to_dm_9000_eth_ctrl_eth_fpga`	`cyclone_II_0_sdram_clk_to_SDRAM_8MB_sdram_clk`






`clock_oscillator_0_clk_out_to_cyclone_II_0_clk_in`	`cyclone_II_0_sram_if_to_unnamed_1_sram_if`






`cyclone_II_0_sram_if_to_unnamed_1_sram_if`	`clock_oscillator_0_clk_out_to_cyclone_II_0_clk_in`






`cyclone_II_0_sdram_clk_to_SDRAM_8MB_sdram_clk`	`cyclone_II_0_DM9000A_to_dm_9000_eth_ctrl_eth_fpga`






`cyclone_II_0_sdram_if_to_SDRAM_8MB_sdram_if`	`push_buttons_0_button_17_to_cyclone_II_0_rst_n`









Line 190...	Line 190...