| Line 4... |
Line 4... |
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : tb_dct_cpu.vhd
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-- File : tb_dct_cpu.vhd
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-- Author :
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-- Author :
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-- Company :
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-- Company :
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-- Created : 2006-05-24
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-- Created : 2006-05-24
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-- Last update: 2006-08-22
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-- Last update: 2013-03-22
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-- Platform :
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-- Platform :
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-- Standard : VHDL'87
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description: CPU emulator
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-- Description: CPU emulator
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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| Line 41... |
Line 41... |
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entity tb_dct_cpu is
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entity tb_dct_cpu is
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|
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generic (
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generic (
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data_width_g : integer := 32;
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data_width_g : integer := 32;
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comm_width_g : integer := 3);
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comm_width_g : integer := 5);
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port (
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port (
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clk_dctqidct_fast : in std_logic;
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clk_dctqidct_fast : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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rst_n : in std_logic;
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rst_n : in std_logic;
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| Line 122... |
Line 122... |
signal result_is_quant_r : std_logic;
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signal result_is_quant_r : std_logic;
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signal last_av_r : integer;
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signal last_av_r : integer;
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signal wait_zero_r : std_logic;
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signal wait_zero_r : std_logic;
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|
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signal test_data_type : integer := 0;
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signal test_data_type : integer := 2;
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-- CONTROL WORD CONFIG
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-- CONTROL WORD CONFIG
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signal intra : std_logic := '0';
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signal intra : std_logic := '0';
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-- signal intra_old_r : std_logic;
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-- signal intra_old_r : std_logic;
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signal qp : std_logic_vector(qp_w_c-1 downto 0) := std_logic_vector(to_unsigned(qp_c, qp_w_c));
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signal qp : std_logic_vector(qp_w_c-1 downto 0) := std_logic_vector(to_unsigned(qp_c, qp_w_c));
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| Line 198... |
Line 198... |
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when send_av =>
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when send_av =>
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av_out <= '1';
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av_out <= '1';
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data_out <= std_logic_vector(to_unsigned(hibi_addr_dct_c, data_width_g));
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data_out <= std_logic_vector(to_unsigned(hibi_addr_dct_c, data_width_g));
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we_out <= '1';
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we_out <= '1';
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comm_out <= "010";
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comm_out <= "00010";
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send_ctrl <= send_ret_addr_q;
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send_ctrl <= send_ret_addr_q;
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when send_ret_addr_q =>
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when send_ret_addr_q =>
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if full_in = '0' then
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if full_in = '0' then
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av_out <= '0';
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av_out <= '0';
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| Line 337... |
Line 337... |
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if res_i_cnt_r = data_max_c-values_per_word_c then
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if res_i_cnt_r = data_max_c-values_per_word_c then
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res_i_cnt_r <= 0;
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res_i_cnt_r <= 0;
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data_r.idct <= (others => (others => '0'));
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data_r.idct <= (others => (others => '0'));
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assert false report "IDCT Data received!" severity note;
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assert false report "IDCT Data received!" severity note;
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--new_req_r <= '1'; -- LM to no self
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else
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else
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res_i_cnt_r <= res_i_cnt_r + values_per_word_c;
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res_i_cnt_r <= res_i_cnt_r + values_per_word_c;
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end if;
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end if;
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end if;
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end if;
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