URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [ip_xact/] [hibi_wrapper_r4.3.0.xml] - Diff between revs 145 and 149

Rev 145	Rev 149
Line 1...	Line 1...






`TUT`	`TUT`
`ip.hwp.communication`	`ip.hwp.communication`
`hibi_wrapper_r4`	`hibi_wrapper_r4`
`3.0`	`3.0`
Line 846...	Line 846...





`debug_in`

`in`


`std_logic_vector`
`IEEE.std_logic_1164.all`
`rtl`



`(others => '0')`







`debug_out`	`debug_out`

`out`	`out`


Line 891...	Line 872...
`0`	`0`





	`debug_in`

	`in`

	`1`
	`0`



	`std_logic_vector`
	`IEEE.std_logic_1164.all`
	`rtl`



	`(others => '0')`







`addr_g`	`addr_g`
`addressing settings: unique for each wrapper`	`addressing settings: unique for each wrapper`
Line 941...	Line 943...
`32`	`32`


`debug_width_g`	`debug_width_g`
`For special monitors`	`For special monitors`
`0`	`2`


`fifo_sel_g`	`fifo_sel_g`
`fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)`	`fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)`
`0`	`0`
Line 991...	Line 993...
`4`	`4`


`n_cfg_pages_g`	`n_cfg_pages_g`
`Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages`	`Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages`
`0`	`1`


`n_extra_params_g`	`n_extra_params_g`
`app-specific registers`	`app-specific registers`
`0`	`0`