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-- ***************************************************
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-- ***************************************************
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-- File: hibi_segment.vhd
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-- File: hibi_segment.vhd
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-- Creation date: 02.07.2012
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-- Creation date: 21.11.2012
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-- Creation time: 15:39:00
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-- Creation time: 16:02:46
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-- Description:
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-- Description:
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-- Created by: matilail
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-- Created by: matilail
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-- This file was generated with Kactus2 vhdl generator.
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-- This file was generated with Kactus2 vhdl generator.
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-- ***************************************************
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-- ***************************************************
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library IEEE;
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library IEEE;
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| Line 14... |
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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entity hibi_segment is
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entity hibi_segment is
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generic (
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generic (
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hibi_addr_0_g : integer := 16#01000000#; -- HIBI address for interface 0
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ip_mslave_0_addr_end : integer := 2; -- HIBI end address for interface 0
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hibi_addr_1_g : integer := 16#03000000#; -- HIBI address for interface 1
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ip_mslave_0_addr_start : integer := 1; -- HIBI address for interface 0
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hibi_addr_2_g : integer := 16#05000000#; -- HIBI address for interface 2
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ip_mslave_1_addr_end : integer := 4; -- HIBI end address for interface 1
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hibi_addr_3_g : integer := 16#07000000# -- HIBI address for interface 3
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ip_mslave_1_addr_start : integer := 3; -- HIBI address for interface 1
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ip_mslave_2_addr_end : integer := 6; -- HIBI end address for interface 2
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ip_mslave_2_addr_start : integer := 5; -- HIBI address for interface 2
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ip_mslave_3_addr_end : integer := 8; -- HIBI end address for interface 3
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ip_mslave_3_addr_start : integer := 7 -- HIBI address for interface 3
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);
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);
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port (
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port (
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-- Interface: clocks_0
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-- Interface: clocks_0
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| Line 134... |
Line 138... |
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architecture structural of hibi_segment is
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architecture structural of hibi_segment is
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV : std_logic;
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV : std_logic;
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signal hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveAV : std_logic;
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signal hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2AV : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV : std_logic;
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signal hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV : std_logic;
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signal hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV : std_logic;
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM : std_logic_vector(4 downto 0);
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM : std_logic_vector(4 downto 0);
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signal hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveCOMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2COMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM : std_logic_vector(4 downto 0);
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signal hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM : std_logic_vector(4 downto 0);
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signal hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM : std_logic_vector(4 downto 0);
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA : std_logic_vector(31 downto 0);
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA : std_logic_vector(31 downto 0);
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signal hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveDATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2DATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA : std_logic_vector(31 downto 0);
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signal hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA : std_logic_vector(31 downto 0);
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signal hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA : std_logic_vector(31 downto 0);
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL : std_logic;
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL : std_logic;
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signal hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveFULL : std_logic;
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signal hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2FULL : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL : std_logic;
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signal hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL : std_logic;
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signal hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL : std_logic;
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK : std_logic;
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signal hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK : std_logic;
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signal hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK : std_logic;
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signal hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveLOCK : std_logic;
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signal hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2LOCK : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK : std_logic;
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signal hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK : std_logic;
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signal hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK : std_logic;
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signal hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK : std_logic;
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component hibi_orbus_small
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component hibi_orbus_small
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generic (
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generic (
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comm_width_g : integer := 5; -- HIBI command width
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comm_width_g : integer := 5; -- HIBI command width
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data_width_g : integer := 32 -- HIBI data width
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data_width_g : integer := 32 -- HIBI data width
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| Line 221... |
Line 225... |
cfg_re_g : integer := 0; -- enable reading config
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cfg_re_g : integer := 0; -- enable reading config
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cfg_we_g : integer := 0; -- enable writing config
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cfg_we_g : integer := 0; -- enable writing config
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comm_width_g : integer := 5; -- HIBI communication width (HIBI v.2=3, v.3 = 5 bits)
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comm_width_g : integer := 5; -- HIBI communication width (HIBI v.2=3, v.3 = 5 bits)
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counter_width_g : integer := 7; -- greater than or equal (n_agents, max_send...)
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counter_width_g : integer := 7; -- greater than or equal (n_agents, max_send...)
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data_width_g : integer := 32; -- HIBI data width (less than or equal)
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data_width_g : integer := 32; -- HIBI data width (less than or equal)
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debug_width_g : integer := 0; -- For special monitors
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debug_width_g : integer := 2; -- For special monitors
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fifo_sel_g : integer := 0; -- fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)
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fifo_sel_g : integer := 0; -- fifo_sel: 0 synch multiclk, 1 basic GALS, 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)
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id_g : integer := 5; -- used instead of addr in recfg
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id_g : integer := 5; -- used instead of addr in recfg
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id_max_g : integer := 0; -- Only for bridges+cfg, zero for others!
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id_max_g : integer := 0; -- Only for bridges+cfg, zero for others!
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id_min_g : integer := 0; -- Only for bridges+cfg, zero for others!
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id_min_g : integer := 0; -- Only for bridges+cfg, zero for others!
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id_width_g : integer := 4; -- gte(log2(id_g))
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id_width_g : integer := 4; -- gte(log2(id_g))
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inv_addr_en_g : integer := 0; -- Only for bridges
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inv_addr_en_g : integer := 0; -- Only for bridges
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keep_slot_g : integer := 0; -- for TDMA
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keep_slot_g : integer := 0; -- for TDMA
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max_send_g : integer := 50; -- in words. Max_send can be wrapper-specific.
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max_send_g : integer := 50; -- in words. Max_send can be wrapper-specific.
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n_agents_g : integer := 4; -- Number of agents within one segment. Ensure that all wrappers in a segment agree on n_agents
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n_agents_g : integer := 4; -- Number of agents within one segment. Ensure that all wrappers in a segment agree on n_agents
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n_cfg_pages_g : integer := 0; -- Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages
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n_cfg_pages_g : integer := 1; -- Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages
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n_extra_params_g : integer := 0; -- app-specific registers
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n_extra_params_g : integer := 0; -- app-specific registers
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n_time_slots_g : integer := 0; -- TDMA is enabled by setting n_time_slots > 0
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n_time_slots_g : integer := 0; -- TDMA is enabled by setting n_time_slots > 0
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prior_g : integer := 2; -- lte n_agents
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prior_g : integer := 2; -- lte n_agents
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rel_agent_freq_g : integer := 1; -- Synch_multiclk FIFOs must know the ratio of frequencies
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rel_agent_freq_g : integer := 1; -- Synch_multiclk FIFOs must know the ratio of frequencies
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rel_bus_freq_g : integer := 1; -- Synch_multiclk FIFOs must know the ratio of frequencies
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rel_bus_freq_g : integer := 1; -- Synch_multiclk FIFOs must know the ratio of frequencies
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| Line 287... |
Line 291... |
agent_full_out : out std_logic;
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agent_full_out : out std_logic;
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agent_one_d_out : out std_logic;
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agent_one_d_out : out std_logic;
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agent_one_p_out : out std_logic;
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agent_one_p_out : out std_logic;
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-- These ports are not in any interface
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-- These ports are not in any interface
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debug_in : in std_logic_vector(0 downto 0);
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debug_in : in std_logic_vector(1 downto 0);
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-- debug_out : out std_logic_vector(0 downto 0);
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-- debug_out : out std_logic_vector(0 downto 0);
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-- Interface: rst_n
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-- Interface: rst_n
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rst_n : in std_logic
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rst_n : in std_logic
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Line 317... |
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hibi_orbus_0 : hibi_orbus_small
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hibi_orbus_0 : hibi_orbus_small
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port map (
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port map (
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bus_av_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV,
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bus_av_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV,
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bus_av_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV,
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bus_av_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV,
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bus_av_2_in => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveAV,
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bus_av_2_in => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2AV,
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bus_av_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV,
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bus_av_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV,
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bus_av_out => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV,
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bus_av_out => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV,
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bus_comm_0_in(4 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM(4 downto 0),
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bus_comm_0_in(4 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM(4 downto 0),
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bus_comm_1_in(4 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM(4 downto 0),
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bus_comm_1_in(4 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM(4 downto 0),
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bus_comm_2_in(4 downto 0) => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveCOMM(4 downto 0),
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bus_comm_2_in(4 downto 0) => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2COMM(4 downto 0),
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bus_comm_3_in(4 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM(4 downto 0),
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bus_comm_3_in(4 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM(4 downto 0),
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bus_comm_out(4 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM(4 downto 0),
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bus_comm_out(4 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM(4 downto 0),
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bus_data_0_in(31 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA(31 downto 0),
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bus_data_0_in(31 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA(31 downto 0),
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bus_data_1_in(31 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA(31 downto 0),
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bus_data_1_in(31 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA(31 downto 0),
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bus_data_2_in(31 downto 0) => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveDATA(31 downto 0),
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bus_data_2_in(31 downto 0) => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2DATA(31 downto 0),
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bus_data_3_in(31 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA(31 downto 0),
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bus_data_3_in(31 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA(31 downto 0),
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bus_data_out(31 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA(31 downto 0),
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bus_data_out(31 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA(31 downto 0),
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bus_full_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL,
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bus_full_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL,
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bus_full_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL,
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bus_full_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL,
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bus_full_2_in => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveFULL,
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bus_full_2_in => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2FULL,
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bus_full_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL,
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bus_full_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL,
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bus_full_out => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL,
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bus_full_out => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL,
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bus_lock_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK,
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bus_lock_0_in => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK,
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bus_lock_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK,
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bus_lock_1_in => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK,
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bus_lock_2_in => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveLOCK,
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bus_lock_2_in => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2LOCK,
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bus_lock_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK,
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bus_lock_3_in => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK,
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bus_lock_out => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK
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bus_lock_out => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK
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);
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);
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hibi_wrapper_r4_0 : hibi_wrapper_r4
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hibi_wrapper_r4_0 : hibi_wrapper_r4
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generic map (
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generic map (
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addr_g => hibi_addr_0_g
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addr_g => ip_mSlave_0_addr_start,
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addr_limit_g => ip_mSlave_0_addr_end
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)
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)
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port map (
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port map (
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agent_av_in => agent_av_in,
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agent_av_in => agent_av_in,
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agent_av_out => agent_av_out,
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agent_av_out => agent_av_out,
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agent_clk => agent_clk,
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agent_clk => agent_clk,
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| Line 357... |
Line 362... |
agent_one_d_out => agent_one_d_out,
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agent_one_d_out => agent_one_d_out,
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agent_one_p_out => agent_one_p_out,
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agent_one_p_out => agent_one_p_out,
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agent_re_in => agent_re_in,
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agent_re_in => agent_re_in,
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agent_sync_clk => agent_sync_clk,
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agent_sync_clk => agent_sync_clk,
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agent_we_in => agent_we_in,
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agent_we_in => agent_we_in,
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bus_av_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV,
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bus_av_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV,
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bus_av_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV,
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bus_av_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveAV,
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bus_clk => bus_clk,
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bus_clk => bus_clk,
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bus_comm_in(4 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM(4 downto 0),
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bus_comm_in(4 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM(4 downto 0),
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bus_comm_out(4 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM(4 downto 0),
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bus_comm_out(4 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveCOMM(4 downto 0),
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bus_data_in(31 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA(31 downto 0),
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bus_data_in(31 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA(31 downto 0),
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bus_data_out(31 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA(31 downto 0),
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bus_data_out(31 downto 0) => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveDATA(31 downto 0),
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bus_full_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL,
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bus_full_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL,
|
bus_full_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL,
|
bus_full_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveFULL,
|
bus_lock_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK,
|
bus_lock_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK,
|
bus_lock_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK,
|
bus_lock_out => hibi_orbus_0_slave_0_to_hibi_wrapper_r4_0_bus_mSlaveLOCK,
|
bus_sync_clk => bus_sync_clk,
|
bus_sync_clk => bus_sync_clk,
|
debug_in => (others => '0'),
|
debug_in => (others => '0'),
|
rst_n => rst_n
|
rst_n => rst_n
|
);
|
);
|
|
|
hibi_wrapper_r4_1 : hibi_wrapper_r4
|
hibi_wrapper_r4_1 : hibi_wrapper_r4
|
generic map (
|
generic map (
|
addr_g => hibi_addr_1_g
|
addr_g => ip_mSlave_1_addr_start,
|
|
addr_limit_g => ip_mSlave_1_addr_end
|
)
|
)
|
port map (
|
port map (
|
agent_av_in => agent_av_in_1,
|
agent_av_in => agent_av_in_1,
|
agent_av_out => agent_av_out_1,
|
agent_av_out => agent_av_out_1,
|
agent_clk => agent_clk_1,
|
agent_clk => agent_clk_1,
|
| Line 392... |
Line 398... |
agent_one_d_out => agent_one_d_out_1,
|
agent_one_d_out => agent_one_d_out_1,
|
agent_one_p_out => agent_one_p_out_1,
|
agent_one_p_out => agent_one_p_out_1,
|
agent_re_in => agent_re_in_1,
|
agent_re_in => agent_re_in_1,
|
agent_sync_clk => agent_sync_clk_1,
|
agent_sync_clk => agent_sync_clk_1,
|
agent_we_in => agent_we_in_1,
|
agent_we_in => agent_we_in_1,
|
bus_av_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV,
|
bus_av_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV,
|
bus_av_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV,
|
bus_av_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1AV,
|
bus_clk => bus_clk_1,
|
bus_clk => bus_clk_1,
|
bus_comm_in(4 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM(4 downto 0),
|
bus_comm_in(4 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1COMM(4 downto 0),
|
bus_data_in(31 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA(31 downto 0),
|
bus_data_in(31 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1DATA(31 downto 0),
|
bus_full_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL,
|
bus_full_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL,
|
bus_full_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL,
|
bus_full_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1FULL,
|
bus_lock_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK,
|
bus_lock_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK,
|
bus_lock_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK,
|
bus_lock_out => hibi_wrapper_r4_1_bus_mSlave_to_hibi_orbus_0_slave_1LOCK,
|
bus_sync_clk => bus_sync_clk_1,
|
bus_sync_clk => bus_sync_clk_1,
|
debug_in => (others => '0'),
|
debug_in => (others => '0'),
|
rst_n => rst_n
|
rst_n => rst_n
|
);
|
);
|
|
|
hibi_wrapper_r4_2 : hibi_wrapper_r4
|
hibi_wrapper_r4_2 : hibi_wrapper_r4
|
generic map (
|
generic map (
|
addr_g => hibi_addr_2_g
|
addr_g => ip_mSlave_2_addr_start,
|
|
addr_limit_g => ip_mSlave_2_addr_end
|
)
|
)
|
port map (
|
port map (
|
agent_av_in => agent_av_in_2,
|
agent_av_in => agent_av_in_2,
|
agent_av_out => agent_av_out_2,
|
agent_av_out => agent_av_out_2,
|
agent_clk => agent_clk_2,
|
agent_clk => agent_clk_2,
|
| Line 427... |
Line 434... |
agent_one_d_out => agent_one_d_out_2,
|
agent_one_d_out => agent_one_d_out_2,
|
agent_one_p_out => agent_one_p_out_2,
|
agent_one_p_out => agent_one_p_out_2,
|
agent_re_in => agent_re_in_2,
|
agent_re_in => agent_re_in_2,
|
agent_sync_clk => agent_sync_clk_2,
|
agent_sync_clk => agent_sync_clk_2,
|
agent_we_in => agent_we_in_2,
|
agent_we_in => agent_we_in_2,
|
bus_av_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV,
|
bus_av_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV,
|
bus_av_out => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveAV,
|
bus_av_out => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2AV,
|
bus_clk => bus_clk_2,
|
bus_clk => bus_clk_2,
|
bus_comm_in(4 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM(4 downto 0),
|
bus_comm_in(4 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveCOMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2COMM(4 downto 0),
|
bus_data_in(31 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA(31 downto 0),
|
bus_data_in(31 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveDATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2DATA(31 downto 0),
|
bus_full_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL,
|
bus_full_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL,
|
bus_full_out => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveFULL,
|
bus_full_out => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2FULL,
|
bus_lock_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK,
|
bus_lock_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK,
|
bus_lock_out => hibi_orbus_0_slave_2_to_hibi_wrapper_r4_2_bus_mSlaveLOCK,
|
bus_lock_out => hibi_wrapper_r4_2_bus_mSlave_to_hibi_orbus_0_slave_2LOCK,
|
bus_sync_clk => bus_sync_clk_2,
|
bus_sync_clk => bus_sync_clk_2,
|
debug_in => (others => '0'),
|
debug_in => (others => '0'),
|
rst_n => rst_n
|
rst_n => rst_n
|
);
|
);
|
|
|
hibi_wrapper_r4_3 : hibi_wrapper_r4
|
hibi_wrapper_r4_3 : hibi_wrapper_r4
|
generic map (
|
generic map (
|
addr_g => hibi_addr_3_g
|
addr_g => ip_mSlave_3_addr_start,
|
|
addr_limit_g => ip_mSlave_3_addr_end
|
)
|
)
|
port map (
|
port map (
|
agent_av_in => agent_av_in_3,
|
agent_av_in => agent_av_in_3,
|
agent_av_out => agent_av_out_3,
|
agent_av_out => agent_av_out_3,
|
agent_clk => agent_clk_3,
|
agent_clk => agent_clk_3,
|
| Line 462... |
Line 470... |
agent_one_d_out => agent_one_d_out_3,
|
agent_one_d_out => agent_one_d_out_3,
|
agent_one_p_out => agent_one_p_out_3,
|
agent_one_p_out => agent_one_p_out_3,
|
agent_re_in => agent_re_in_3,
|
agent_re_in => agent_re_in_3,
|
agent_sync_clk => agent_sync_clk_3,
|
agent_sync_clk => agent_sync_clk_3,
|
agent_we_in => agent_we_in_3,
|
agent_we_in => agent_we_in_3,
|
bus_av_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterAV,
|
bus_av_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterAV,
|
bus_av_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV,
|
bus_av_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3AV,
|
bus_clk => bus_clk_3,
|
bus_clk => bus_clk_3,
|
bus_comm_in(4 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterCOMM(4 downto 0),
|
bus_comm_in(4 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterCOMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM(4 downto 0),
|
bus_comm_out(4 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3COMM(4 downto 0),
|
bus_data_in(31 downto 0) => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterDATA(31 downto 0),
|
bus_data_in(31 downto 0) => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterDATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA(31 downto 0),
|
bus_data_out(31 downto 0) => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3DATA(31 downto 0),
|
bus_full_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterFULL,
|
bus_full_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterFULL,
|
bus_full_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL,
|
bus_full_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3FULL,
|
bus_lock_in => hibi_orbus_0_master_to_hibi_wrapper_r4_0_bus_mMasterLOCK,
|
bus_lock_in => hibi_wrapper_r4_2_bus_mMaster_to_hibi_orbus_0_masterLOCK,
|
bus_lock_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK,
|
bus_lock_out => hibi_wrapper_r4_3_bus_mSlave_to_hibi_orbus_0_slave_3LOCK,
|
bus_sync_clk => bus_sync_clk_3,
|
bus_sync_clk => bus_sync_clk_3,
|
debug_in => (others => '0'),
|
debug_in => (others => '0'),
|
rst_n => rst_n
|
rst_n => rst_n
|
);
|
);
|
