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-- ***************************************************
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-- ***************************************************
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-- File: basic_tester_hibi_example.vhd
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-- File: basic_tester_hibi_example.vhd
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-- Creation date: 02.07.2012
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-- Creation date: 21.11.2012
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-- Creation time: 15:50:14
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-- Creation time: 14:28:17
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-- Description: Simple example on how to use basic_tester with hibi.
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-- Description: Simple example on how to use basic_tester with hibi.
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-- Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
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-- Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
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--
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--
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-- Tx sends few words to rx which takes and checks them.
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-- Tx sends few words to rx which takes and checks them.
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-- Basic_tester is meant for simulation only.
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-- Basic_tester is meant for simulation only.
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM : std_logic_vector(4 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM : std_logic_vector(4 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA : std_logic_vector(31 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA : std_logic_vector(31 downto 0);
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D : std_logic;
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signal basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D : std_logic;
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signal basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE : std_logic;
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signal basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE : std_logic;
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signal clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK : std_logic;
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signal clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK : std_logic;
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signal rst_r_nRESETn : std_logic;
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signal rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV : std_logic;
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM : std_logic_vector(4 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM : std_logic_vector(4 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA : std_logic_vector(31 downto 0);
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signal hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA : std_logic_vector(31 downto 0);
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P : std_logic;
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signal hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P : std_logic;
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| Line 112... |
Line 112... |
);
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);
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end component;
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end component;
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component hibi_segment
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component hibi_segment
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generic (
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generic (
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hibi_addr_0_g : integer := 16#01000000#; -- HIBI address for interface 0
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ip_mslave_0_addr_end : integer := 2; -- HIBI end address for interface 0
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hibi_addr_1_g : integer := 16#03000000#; -- HIBI address for interface 1
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ip_mslave_0_addr_start : integer := 1; -- HIBI address for interface 0
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hibi_addr_2_g : integer := 16#05000000#; -- HIBI address for interface 2
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ip_mslave_1_addr_end : integer := 4; -- HIBI end address for interface 1
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hibi_addr_3_g : integer := 16#07000000# -- HIBI address for interface 3
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ip_mslave_1_addr_start : integer := 3; -- HIBI address for interface 1
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ip_mslave_2_addr_end : integer := 6; -- HIBI end address for interface 2
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ip_mslave_2_addr_start : integer := 5; -- HIBI address for interface 2
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ip_mslave_3_addr_end : integer := 8; -- HIBI end address for interface 3
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ip_mslave_3_addr_start : integer := 7 -- HIBI address for interface 3
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);
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);
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port (
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port (
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-- Interface: clocks_0
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-- Interface: clocks_0
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Line 140... |
bus_clk_1 : in std_logic;
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bus_clk_1 : in std_logic;
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bus_sync_clk_1 : in std_logic;
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bus_sync_clk_1 : in std_logic;
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-- Interface: clocks_2
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-- Interface: clocks_2
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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-- agent_clk_2 : in std_logic;
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agent_clk_2 : in std_logic;
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-- agent_sync_clk_2 : in std_logic;
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agent_sync_clk_2 : in std_logic;
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-- bus_clk_2 : in std_logic;
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bus_clk_2 : in std_logic;
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bus_sync_clk_2 : in std_logic;
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bus_sync_clk_2 : in std_logic;
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-- Interface: clocks_3
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-- Interface: clocks_3
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-- Clock inputs interface for hibi wrapper_3
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-- Clock inputs interface for hibi wrapper_3
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-- agent_clk_3 : in std_logic;
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agent_clk_3 : in std_logic;
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-- agent_sync_clk_3 : in std_logic;
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agent_sync_clk_3 : in std_logic;
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-- bus_clk_3 : in std_logic;
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bus_clk_3 : in std_logic;
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bus_sync_clk_3 : in std_logic;
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bus_sync_clk_3 : in std_logic;
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-- Interface: ip_mMaster_0
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-- Interface: ip_mMaster_0
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-- HIBI ip mirrored master agent interface 0 (r4 wrapper)
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-- HIBI ip mirrored master agent interface 0 (r4 wrapper)
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agent_av_in : in std_logic;
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agent_av_in : in std_logic;
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| Line 280... |
Line 284... |
agent_comm_in(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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agent_comm_in(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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agent_data_in(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
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agent_data_in(31 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1DATA(31 downto 0),
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agent_empty_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
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agent_empty_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1EMPTY,
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agent_one_d_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
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agent_one_d_in => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1ONE_D,
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agent_re_out => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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agent_re_out => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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rst_n => rst_r_nRESETn
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rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
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);
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);
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basic_tester_tx_0 : basic_tester_tx
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basic_tester_tx_0 : basic_tester_tx
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generic map (
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generic map (
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conf_file_g => "test_tx.txt"
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conf_file_g => "test_tx.txt"
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| Line 295... |
Line 299... |
agent_comm_out(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_comm_out(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_data_out(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
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agent_data_out(31 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterDATA(31 downto 0),
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agent_full_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
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agent_full_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveFULL,
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agent_one_p_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_one_p_in => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_we_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
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agent_we_out => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
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clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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rst_n => rst_r_nRESETn
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rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
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);
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);
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clk_gen_0 : clk_gen
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clk_gen_0 : clk_gen
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port map (
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port map (
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clk_out => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK
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clk_out => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK
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);
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);
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hibi_segment_0 : hibi_segment(structural)
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hibi_segment_0 : hibi_segment
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generic map (
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hibi_addr_0_g => 16#07000000#,
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hibi_addr_1_g => 16#05000000#,
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hibi_addr_2_g => 16#03000000#,
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hibi_addr_3_g => 16#01000000#
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)
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port map (
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port map (
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agent_av_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
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agent_av_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterAV,
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agent_av_in_1 => '0',
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agent_av_in_1 => '0',
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agent_av_in_2 => '0',
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agent_av_in_2 => '0',
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agent_av_in_3 => '0',
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agent_av_in_3 => '0',
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agent_av_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
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agent_av_out_1 => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1AV,
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agent_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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agent_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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agent_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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agent_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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agent_clk_2 => '0',
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agent_clk_3 => '0',
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agent_comm_in(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_comm_in(4 downto 0) => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterCOMM(4 downto 0),
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agent_comm_in_1 => (others => '0'),
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agent_comm_in_1 => (others => '0'),
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agent_comm_in_2 => (others => '0'),
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agent_comm_in_2 => (others => '0'),
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agent_comm_in_3 => (others => '0'),
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agent_comm_in_3 => (others => '0'),
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agent_comm_out_1(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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agent_comm_out_1(4 downto 0) => basic_tester_rx_0_hibi_slave_to_hibi_segment_0_ip_mSlave_1COMM(4 downto 0),
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| Line 337... |
Line 337... |
agent_one_p_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_one_p_out => hibi_segment_0_ip_mSlave_0_to_basic_tester_tx_0_hibi_slaveONE_P,
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agent_re_in => '0',
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agent_re_in => '0',
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agent_re_in_1 => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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agent_re_in_1 => basic_tester_rx_0_hibi_master_to_hibi_segment_0_ip_mMaster_1RE,
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agent_re_in_2 => '0',
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agent_re_in_2 => '0',
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agent_re_in_3 => '0',
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agent_re_in_3 => '0',
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agent_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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agent_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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agent_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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agent_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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agent_sync_clk_2 => '0',
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agent_sync_clk_3 => '0',
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agent_we_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
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agent_we_in => hibi_segment_0_ip_mMaster_0_to_basic_tester_tx_0_hibi_masterWE,
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agent_we_in_1 => '0',
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agent_we_in_1 => '0',
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agent_we_in_2 => '0',
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agent_we_in_2 => '0',
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agent_we_in_3 => '0',
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agent_we_in_3 => '0',
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bus_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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bus_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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bus_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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bus_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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bus_sync_clk => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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bus_clk_2 => '0',
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bus_sync_clk_1 => clk_gen_0_Generated_clk_to_basic_tester_tx_0_clockCLK,
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bus_clk_3 => '0',
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bus_sync_clk => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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bus_sync_clk_1 => clk_gen_0_Generated_hibi_clk_to_hibi_segment_0_clocks_0AGENT_SYNC_CLK,
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bus_sync_clk_2 => '0',
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bus_sync_clk_2 => '0',
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bus_sync_clk_3 => '0',
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bus_sync_clk_3 => '0',
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rst_n => rst_r_nRESETn
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rst_n => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
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);
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);
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rst_gen_0 : rst_gen
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rst_gen_0 : rst_gen
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port map (
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port map (
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rst_n_out => rst_r_nRESETn
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rst_n_out => rst_gen_0_Generated_reset_to_hibi_segment_0_rst_nRESETn
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);
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);
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end structural_seg;
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end structural_seg;
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No newline at end of file
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No newline at end of file
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