OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp_flood_example_dm9000a/] [1.0/] [ip_xact/] [udp_flood_example_dm9000a.1.0.xml] - Diff between revs 145 and 157

Show entire file | Details | Blame | View Log

Rev 145 Rev 157
Line 1... Line 1...
 
 
 
 
 
 
 
 
 
 
 
 
        TUT
        TUT
        soc
        soc
        udp_flood_example_dm9000a
        udp_flood_example_dm9000a
        1.0
        1.0
Line 84... Line 87...
                        
                        
                        8
                        8
                        little
                        little
                
                
                
                
                        clk_in
 
                        Clock input.
 
                        
 
                        
 
                        
 
                        false
 
                        
 
                                
 
                                        
 
                                                CLK
 
                                        
 
                                        
 
                                                clk_in_CLK
 
                                        
 
                                
 
                        
 
                        8
 
                        little
 
                
 
                
 
                        link_up_out
                        link_up_out
                        1-bit status
                        1-bit status
                        
                        
                        
                        
                        
                        
Line 143... Line 126...
                                
                                
                        
                        
                        8
                        8
                        little
                        little
                
                
 
                
 
                        clk_in
 
                        Clock input.
 
                        
 
                        
 
                        
 
                        false
 
                        
 
                                
 
                                        
 
                                                CLK
 
                                        
 
                                        
 
                                                clk_in_CLK
 
                                        
 
                                
 
                        
 
                        8
 
                        little
 
                
        
        
        
        
                
                
                        
                        
                                kactusHierarchical
                                kactusHierarchical
Line 397... Line 400...
                        Pin map settings that will be used by Quartus genrator.
                        Pin map settings that will be used by Quartus genrator.
                        
                        
                                ../../../../ip.hwp.interface/udp_ip/1.0/syn/udp_ip_dm9000a_de2_assignments.qsf
                                ../../../../ip.hwp.interface/udp_ip/1.0/syn/udp_ip_dm9000a_de2_assignments.qsf
                                quartusPinmap
                                quartusPinmap
                                false
                                false
                                
 
                                        false
 
                                
 
                        
                        
                
                
                
                
                        simulation
                        simulation
                        
                        
                                ../sim/sim.do
                                ../sim/sim.do
                                modelsimScript
                                modelsimScript
                                false
                                false
                                
 
                                        false
 
                                
 
                                Executes simulation. Uses force commands to create clock and reset.
                                Executes simulation. Uses force commands to create clock and reset.
 
 
Note that PLL requires simulation resolution of 1 ps.
Note that PLL requires simulation resolution of 1 ps.
                        
                        
                        
                        
                                ../sim/all_waves.do
                                ../sim/all_waves.do
                                modelsimScript
                                modelsimScript
                                false
                                false
                                
 
                                        false
 
                                
 
                                Adds the necessary signals to wave window and formats them. Called by sim.do.
                                Adds the necessary signals to wave window and formats them. Called by sim.do.
                        
                        
                        
                        
                                ../sim/compile_all.do
                                ../sim/compile_all.do
                                modelsimScript
                                modelsimScript
                                false
                                false
                                
 
                                        false
 
                                
 
                                Compile "all" VHDL files (except Altera's simulation models).
                                Compile "all" VHDL files (except Altera's simulation models).
 
 
                        
                        
                        
                        
                                ../sim/compile_altera.do
                                ../sim/compile_altera.do
                                modelsimScript
                                modelsimScript
                                false
                                false
                                
 
                                        false
 
                                
 
                                Compiles Altera's simulation models.
                                Compiles Altera's simulation models.
 
 
Please edit the path definitions to match your Quartus installation directory.
Please edit the path definitions to match your Quartus installation directory.
                        
                        
                        
                        
Line 457... Line 445...
                        doc
                        doc
                        
                        
                                ../doc/setup.pptx
                                ../doc/setup.pptx
                                powerPoint
                                powerPoint
                                false
                                false
                                
 
                                        false
 
                                
 
                        
                        
                
                
        
        
        
        
                
                

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.