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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [udp_flood_example_dm9000a/] [1.0/] [vhd/] [udp_flood_example_dm9000a.vhd] - Diff between revs 145 and 157

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-- ***************************************************
-- ***************************************************
-- File: udp_flood_example_dm9000a.vhd
-- File: udp_flood_example_dm9000a.vhd
-- Creation date: 05.04.2012
-- Creation date: 18.01.2013
-- Creation time: 13:38:38
-- Creation time: 12:46:22
-- Description: Simple example to test the connection FPGA -> PC.
-- Description: Simple example to test the connection FPGA -> PC.
-- 
-- 
-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
-- Created by: ege
-- Created by: matilail
-- This file was generated with Kactus2 vhdl generator.
-- This file was generated with Kactus2 vhdl generator.
-- ***************************************************
-- ***************************************************
library IEEE;
library IEEE;
library work;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_1164.all;

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