-- Description: Simple example to test the connection FPGA -> PC.
-- Description: Simple example to test the connection FPGA -> PC.
--
--
-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
-- Flooder unit sends all the time, UDP/IP block transfers them to PC. Designer can use netstat, netcat, wireshark or similar to catch the packet at the PC's end.
-- Created by: ege
-- Created by: matilail
-- This file was generated with Kactus2 vhdl generator.
-- This file was generated with Kactus2 vhdl generator.