| Line 64... |
Line 64... |
end G729A_ASIP_REGFILE_16X16_2W;
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end G729A_ASIP_REGFILE_16X16_2W;
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architecture ARC of G729A_ASIP_REGFILE_16X16_2W is
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architecture ARC of G729A_ASIP_REGFILE_16X16_2W is
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constant REGNUM : natural := 16;
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constant REGNUM : natural := 16;
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constant ZERO : std_logic_vector(SDLEN-1 downto 0) := (others => '0');
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subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
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subtype WORD_T is std_logic_vector(SDLEN-1 downto 0);
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type MEM_T is array (REGNUM/2-1 downto 0) of WORD_T;
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type MEM_T is array (REGNUM/2-1 downto 0) of WORD_T;
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type RID_VEC_T is array (natural range <>) of RID_T;
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type WORD_VEC_T is array (natural range <>) of WORD_T;
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signal REG_EVEN,REG_ODD : MEM_T;
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signal REG_EVEN,REG_ODD : MEM_T;
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signal WE0_EVEN,WE0_ODD : std_logic;
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signal WE0_EVEN,WE0_ODD : std_logic;
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signal WE1_EVEN,WE1_ODD : std_logic;
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signal WE1_EVEN,WE1_ODD : std_logic;
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signal IWA0,IWA1 : natural range 0 to REGNUM/2-1;
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signal IWA0,IWA1 : natural range 0 to REGNUM/2-1;
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signal WA0_LSB,WA1_LSB : std_logic;
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signal WA0_LSB,WA1_LSB : std_logic;
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signal IRA0,IRA1,IRA2,IRA3 : natural range 0 to REGNUM/2-1;
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signal IRA0,IRA1,IRA2,IRA3 : natural range 0 to REGNUM/2-1;
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signal RA0_LSB,RA1_LSB,RA2_LSB,RA3_LSB : std_logic;
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signal RA0_LSB,RA1_LSB,RA2_LSB,RA3_LSB : std_logic;
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signal D0_LO,D0_HI : std_logic_vector(SDLEN-1 downto 0);
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signal D0_LO,D0_HI : std_logic_vector(SDLEN-1 downto 0);
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signal WE_EVEN,WE_ODD : std_logic_vector(REGNUM/2-1 downto 0);
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signal D_EVEN,D_ODD : WORD_VEC_T(REGNUM/2-1 downto 0);
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signal D0_EVEN,D0_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal D0_EVEN,D0_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal D1_LO,D1_HI : std_logic_vector(SDLEN-1 downto 0);
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signal D1_LO,D1_HI : std_logic_vector(SDLEN-1 downto 0);
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signal D1_EVEN,D1_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal D1_EVEN,D1_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_EVEN,Q1_EVEN : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_EVEN,Q1_EVEN : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_ODD,Q1_ODD : std_logic_vector(SDLEN-1 downto 0);
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signal Q0_ODD,Q1_ODD : std_logic_vector(SDLEN-1 downto 0);
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| Line 99... |
Line 102... |
---------------------------------------------
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---------------------------------------------
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D0_LO <= D0_i(SDLEN-1 downto 0);
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D0_LO <= D0_i(SDLEN-1 downto 0);
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D0_HI <= D0_i(SDLEN*2-1 downto SDLEN);
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D0_HI <= D0_i(SDLEN*2-1 downto SDLEN);
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D0_EVEN <= D0_LO;
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D0_ODD <= D0_HI when (LW0_i = '1') else D0_LO;
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process(WA0_LSB,WE0_i,LW0_i)
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begin
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if(LW0_i = '0') then
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WE0_EVEN <= (WE0_i and not(WA0_LSB));
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WE0_ODD <= (WE0_i and WA0_LSB);
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else
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WE0_EVEN <= WE0_i;
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WE0_ODD <= WE0_i;
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end if;
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end process;
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---------------------------------------------
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D1_LO <= D1_i(SDLEN-1 downto 0);
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D1_LO <= D1_i(SDLEN-1 downto 0);
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D1_HI <= D1_i(SDLEN*2-1 downto SDLEN);
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D1_HI <= D1_i(SDLEN*2-1 downto SDLEN);
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D1_EVEN <= D1_LO;
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D1_ODD <= D1_HI when (LW1_i = '1') else D1_LO;
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process(WA1_LSB,WE1_i,LW1_i)
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begin
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if(LW1_i = '0') then
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WE1_EVEN <= (WE1_i and not(WA1_LSB));
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WE1_ODD <= (WE1_i and WA1_LSB);
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else
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WE1_EVEN <= WE1_i;
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WE1_ODD <= WE1_i;
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end if;
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end process;
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---------------------------------------------
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---------------------------------------------
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IWA0 <= WA0_i/2;
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IWA0 <= WA0_i/2;
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IWA1 <= WA1_i/2;
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IWA1 <= WA1_i/2;
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WA0_LSB <= GET_LSB(WA0_i);
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WA0_LSB <= GET_LSB(WA0_i);
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WA1_LSB <= GET_LSB(WA1_i);
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WA1_LSB <= GET_LSB(WA1_i);
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process(CLK_i)
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---------------------------------------------
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begin
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if(CLK_i = '1' and CLK_i'event) then
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G0 : for k in 0 to REGNUM/2-1 generate
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if(WE0_EVEN = '1') then
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REG_EVEN(IWA0) <= D0_EVEN;
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WE_EVEN(k) <= '1' when (
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end if;
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(WE0_i = '1' and (IWA0 = k) and (WA0_LSB = '0') and (LW0_i = '0')) or
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if(WE1_EVEN = '1') then
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(WE1_i = '1' and (IWA1 = k) and (WA1_LSB = '0') and (LW1_i = '0')) or
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REG_EVEN(IWA1) <= D1_EVEN;
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(WE0_i = '1' and (IWA0 = k) and (LW0_i = '1')) or
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end if;
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(WE1_i = '1' and (IWA1 = k) and (LW1_i = '1'))
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end if;
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) else '0';
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WE_ODD(k) <= '1' when (
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(WE0_i = '1' and (IWA0 = k) and (WA0_LSB = '1') and (LW0_i = '0')) or
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(WE1_i = '1' and (IWA1 = k) and (WA1_LSB = '1') and (LW1_i = '0')) or
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(WE0_i = '1' and (IWA0 = k) and (LW0_i = '1')) or
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(WE1_i = '1' and (IWA1 = k) and (LW1_i = '1'))
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) else '0';
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process(WE0_i,WE1_i,IWA0,IWA1,WA0_LSB,WA1_LSB,LW0_i,LW1_i,
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D0_LO,D0_HI,D1_LO,D1_HI)
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variable S : natural range 0 to 4-1;
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begin
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-- Write from port #1 must get higher priority because
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-- instruction #1 is newer than instruction #0.
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if(
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(WE1_i = '1') and (IWA1 = k) and
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((WA1_LSB = '0') or (LW1_i = '1'))
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) then
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-- write from port #1
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D_EVEN(k) <= D1_LO;
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else
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-- write from port #0
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D_EVEN(k) <= D0_LO;
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end if;
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if(
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(WE1_i = '1') and (IWA1 = k) and
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(WA1_LSB = '1') and (LW1_i = '0')
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) then
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-- word write from port #1
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S := 0;
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elsif(
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(WE1_i = '1') and (IWA1 = k) and
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(LW1_i = '1')
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) then
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-- long-word write from port #1
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S := 1;
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elsif(
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(WE0_i = '1') and (IWA0 = k) and
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(WA0_LSB = '1') and (LW0_i = '0')
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) then
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-- word write from port #0
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S := 2;
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else
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-- long-word write from port #0
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S := 3;
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end if;
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case S is
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when 0 => D_ODD(k) <= D1_LO;
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when 1 => D_ODD(k) <= D1_HI;
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when 2 => D_ODD(k) <= D0_LO;
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when 3 => D_ODD(k) <= D0_HI;
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end case;
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end process;
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end process;
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process(CLK_i)
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process(CLK_i)
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begin
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begin
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if(CLK_i = '1' and CLK_i'event) then
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if(CLK_i = '1' and CLK_i'event) then
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if(WE0_ODD = '1') then
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if(WE_EVEN(k) = '1') then
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REG_ODD(IWA0) <= D0_ODD;
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REG_EVEN(k) <= D_EVEN(k);
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end if;
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end if;
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if(WE1_ODD = '1') then
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if(WE_ODD(k) = '1') then
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REG_ODD(IWA1) <= D1_ODD;
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REG_ODD(k) <= D_ODD(k);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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---------------------------------------------
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---------------------------------------------
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IRA0 <= RA0_i/2;
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IRA0 <= RA0_i/2;
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IRA1 <= RA1_i/2;
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IRA1 <= RA1_i/2;
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IRA2 <= RA2_i/2;
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IRA2 <= RA2_i/2;
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| Line 243... |
Line 275... |
Q3_o(SDLEN*2-1 downto SDLEN) <= Q3_ODD;
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Q3_o(SDLEN*2-1 downto SDLEN) <= Q3_ODD;
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end if;
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end if;
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end process;
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end process;
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end ARC;
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end ARC;
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