| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- GCpad controller core
|
-- GCpad controller core
|
--
|
--
|
-- $Id: gcpad_ctrl.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $
|
-- $Id: gcpad_ctrl.vhd,v 1.2 2004-10-09 17:04:36 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 58... |
Line 58... |
-- System Interface -------------------------------------------------------
|
-- System Interface -------------------------------------------------------
|
clk_i : in std_logic;
|
clk_i : in std_logic;
|
reset_i : in std_logic;
|
reset_i : in std_logic;
|
pad_request_i : in std_logic;
|
pad_request_i : in std_logic;
|
pad_avail_o : out std_logic;
|
pad_avail_o : out std_logic;
|
|
rx_timeout_o : out std_logic;
|
-- Control Interface ------------------------------------------------------
|
-- Control Interface ------------------------------------------------------
|
tx_start_o : out boolean;
|
tx_start_o : out boolean;
|
tx_finished_i : in boolean;
|
tx_finished_i : in boolean;
|
rx_en_o : out boolean;
|
rx_en_o : out boolean;
|
rx_done_i : in boolean
|
rx_done_i : in boolean;
|
|
rx_data_ok_i : in boolean
|
);
|
);
|
|
|
end gcpad_ctrl;
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end gcpad_ctrl;
|
|
|
|
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| Line 74... |
Line 76... |
|
|
architecture rtl of gcpad_ctrl is
|
architecture rtl of gcpad_ctrl is
|
|
|
type state_t is (IDLE,
|
type state_t is (IDLE,
|
TX,
|
TX,
|
RX_START,
|
RX1_START,
|
RX_WAIT,
|
RX1_WAIT,
|
DEL1,
|
RX2_START,
|
DEL1_WAIT,
|
RX2_WAIT,
|
DEL2,
|
RX3_START,
|
DEL2_WAIT,
|
RX3_WAIT,
|
DEL3,
|
RX4_START,
|
DEL3_WAIT);
|
RX4_WAIT);
|
signal state_s,
|
signal state_s,
|
state_q : state_t;
|
state_q : state_t;
|
|
|
|
signal set_txrx_finished_s : boolean;
|
|
signal enable_txrx_finished_s : boolean;
|
|
signal txrx_finished_q : std_logic;
|
|
|
|
signal timeout_q : std_logic;
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process seq
|
-- Process seq
|
--
|
--
|
| Line 98... |
Line 106... |
seq: process (reset_i, clk_i)
|
seq: process (reset_i, clk_i)
|
begin
|
begin
|
if reset_i = reset_level_g then
|
if reset_i = reset_level_g then
|
state_q <= IDLE;
|
state_q <= IDLE;
|
|
|
|
txrx_finished_q <= '0';
|
|
|
|
timeout_q <= '1';
|
|
|
elsif clk_i'event and clk_i = '1' then
|
elsif clk_i'event and clk_i = '1' then
|
state_q <= state_s;
|
state_q <= state_s;
|
|
|
|
-- transmit/receive finished flag
|
|
if set_txrx_finished_s then
|
|
txrx_finished_q <= '1';
|
|
elsif pad_request_i = '1' then
|
|
txrx_finished_q <= '0';
|
|
end if;
|
|
|
|
if pad_request_i = '1' then
|
|
timeout_q <= '1';
|
|
elsif rx_data_ok_i then
|
|
timeout_q <= '0';
|
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process seq;
|
end process seq;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
| Line 122... |
Line 147... |
pad_request_i)
|
pad_request_i)
|
begin
|
begin
|
rx_en_o <= false;
|
rx_en_o <= false;
|
state_s <= IDLE;
|
state_s <= IDLE;
|
tx_start_o <= false;
|
tx_start_o <= false;
|
pad_avail_o <= '0';
|
set_txrx_finished_s <= false;
|
|
enable_txrx_finished_s <= false;
|
|
|
case state_q is
|
case state_q is
|
when IDLE =>
|
when IDLE =>
|
|
-- enable output of txrx_finished flag
|
|
-- the flag has to be suppressed while the FSM probes four times
|
|
enable_txrx_finished_s <= true;
|
|
|
if pad_request_i = '1' then
|
if pad_request_i = '1' then
|
state_s <= TX;
|
state_s <= TX;
|
tx_start_o <= true;
|
tx_start_o <= true;
|
else
|
else
|
state_s <= IDLE;
|
state_s <= IDLE;
|
| Line 137... |
Line 167... |
|
|
when TX =>
|
when TX =>
|
if not tx_finished_i then
|
if not tx_finished_i then
|
state_s <= TX;
|
state_s <= TX;
|
else
|
else
|
state_s <= RX_START;
|
state_s <= RX1_START;
|
end if;
|
end if;
|
|
|
when RX_START =>
|
when RX1_START =>
|
rx_en_o <= true;
|
rx_en_o <= true;
|
state_s <= RX_WAIT;
|
state_s <= RX1_WAIT;
|
|
|
when RX_WAIT =>
|
when RX1_WAIT =>
|
if rx_done_i then
|
if rx_done_i then
|
state_s <= DEL1;
|
state_s <= RX2_START;
|
else
|
else
|
state_s <= RX_WAIT;
|
state_s <= RX1_WAIT;
|
end if;
|
end if;
|
|
|
when DEL1 =>
|
when RX2_START =>
|
-- start receiver and wait for its initial timeout
|
|
rx_en_o <= true;
|
rx_en_o <= true;
|
state_s <= DEL1_WAIT;
|
state_s <= RX2_WAIT;
|
|
|
when DEL1_WAIT =>
|
when RX2_WAIT =>
|
if rx_done_i then
|
if rx_done_i then
|
state_s <= DEL2;
|
state_s <= RX3_START;
|
else
|
else
|
state_s <= DEL1_WAIT;
|
state_s <= RX2_WAIT;
|
end if;
|
end if;
|
|
|
when DEL2 =>
|
when RX3_START =>
|
-- start receiver and wait for its initial timeout
|
|
rx_en_o <= true;
|
rx_en_o <= true;
|
state_s <= DEL2_WAIT;
|
state_s <= RX3_WAIT;
|
|
|
when DEL2_WAIT =>
|
when RX3_WAIT =>
|
if rx_done_i then
|
if rx_done_i then
|
state_s <= DEL3;
|
state_s <= RX4_START;
|
else
|
else
|
state_s <= DEL2_WAIT;
|
state_s <= RX3_WAIT;
|
end if;
|
end if;
|
|
|
when DEL3 =>
|
when RX4_START =>
|
-- start receiver and wait for its initial timeout
|
|
rx_en_o <= true;
|
rx_en_o <= true;
|
state_s <= DEL3_WAIT;
|
state_s <= RX4_WAIT;
|
|
|
when DEL3_WAIT =>
|
when RX4_WAIT =>
|
if rx_done_i then
|
if rx_done_i then
|
pad_avail_o <= '1';
|
|
state_s <= IDLE;
|
state_s <= IDLE;
|
|
set_txrx_finished_s <= true;
|
else
|
else
|
state_s <= DEL3_WAIT;
|
state_s <= RX4_WAIT;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
null;
|
null;
|
|
|
| Line 197... |
Line 224... |
|
|
end process fsm;
|
end process fsm;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
|
-- Output mapping
|
|
-----------------------------------------------------------------------------
|
|
pad_avail_o <= txrx_finished_q
|
|
when enable_txrx_finished_s else
|
|
'0';
|
|
rx_timeout_o <= timeout_q
|
|
when enable_txrx_finished_s else
|
|
'0';
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.1 2004/10/07 21:23:10 arniml
|
|
-- initial check-in
|
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
