| Line 1... |
Line 1... |
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- GCpad controller core
|
-- GCpad controller core
|
--
|
--
|
-- $Id: gcpad_tx.vhd,v 1.1 2004-10-07 21:23:10 arniml Exp $
|
-- $Id: gcpad_tx.vhd,v 1.2 2004-10-08 20:51:59 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
| Line 62... |
Line 62... |
-- Pad Interface ----------------------------------------------------------
|
-- Pad Interface ----------------------------------------------------------
|
pad_data_o : out std_logic;
|
pad_data_o : out std_logic;
|
-- Control Interface ------------------------------------------------------
|
-- Control Interface ------------------------------------------------------
|
tx_start_i : in boolean;
|
tx_start_i : in boolean;
|
tx_finished_o : out boolean;
|
tx_finished_o : out boolean;
|
tx_size_i : in std_logic_vector( 4 downto 0);
|
tx_size_i : in std_logic_vector( 1 downto 0);
|
tx_command_i : in std_logic_vector(23 downto 0)
|
tx_command_i : in std_logic_vector(23 downto 0)
|
);
|
);
|
|
|
end gcpad_tx;
|
end gcpad_tx;
|
|
|
| Line 117... |
Line 117... |
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implements the sequential elements of this module.
|
-- Implements the sequential elements of this module.
|
--
|
--
|
seq: process (reset_i, clk_i)
|
seq: process (reset_i, clk_i)
|
|
variable size_v : std_logic_vector(num_bits_t'range);
|
begin
|
begin
|
if reset_i = reset_level_g then
|
if reset_i = reset_level_g then
|
command_q <= (others => '1');
|
command_q <= (others => '1');
|
cnt_q <= cnt_long_c;
|
cnt_q <= cnt_long_c;
|
num_bits_q <= (others => '0');
|
num_bits_q <= (others => '0');
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| Line 136... |
Line 137... |
|
|
-- command register and bit counter
|
-- command register and bit counter
|
if load_command_s then
|
if load_command_s then
|
command_q(24 downto 1) <= tx_command_i;
|
command_q(24 downto 1) <= tx_command_i;
|
command_q(0) <= '1';
|
command_q(0) <= '1';
|
num_bits_q <= unsigned(tx_size_i) + 1;
|
|
|
-- workaround for GHDL concatenation
|
|
size_v(num_bits_t'high downto 3) := tx_size_i;
|
|
size_v(2 downto 0) := (others => '0');
|
|
num_bits_q <= unsigned(size_v) + 1;
|
|
|
else
|
else
|
if shift_bits_s then
|
if shift_bits_s then
|
command_q(command_t'high downto 1) <= command_q(command_t'high-1 downto 0);
|
command_q(command_t'high downto 1) <= command_q(command_t'high-1 downto 0);
|
end if;
|
end if;
|
| Line 299... |
Line 304... |
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.1 2004/10/07 21:23:10 arniml
|
|
-- initial check-in
|
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
No newline at end of file
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No newline at end of file
|
