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/* define pinning of the GPIF interface RDY signals
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/* define pinning of the GPIF interface RDY signals
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accessible in the GPIFREADYSTAT register */
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accessible in the GPIFREADYSTAT register */
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#define bmWRX bmBIT0 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmWRX bmBIT0 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmRDYX bmBIT1 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
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#define bmRDYX bmBIT1 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx */
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/* define pinning of the GPIF interface CTL signals
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/* define pinning of the GPIF interface CTL signals
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accessible while the GPIF is in the IDLE state through the
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accessible while the GPIF is in the IDLE state through the
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GPIFIDLECTL register */
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GPIFIDLECTL register */
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#define bmWRU bmBIT1 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmWRU bmBIT1 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */
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#define bmRDYU bmBIT2 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx
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#define bmRDYU bmBIT2 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx */
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/*
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/*
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* Port A (bit addressable):
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* Port A (bit addressable):
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*/
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*/
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