| Line 93... |
Line 93... |
/* check if this is a end of a IN transfer */
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/* check if this is a end of a IN transfer */
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if((flGPIF & bmGPIF_READ_IN_PROGRESS) == bmGPIF_READ_IN_PROGRESS){
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if((flGPIF & bmGPIF_READ_IN_PROGRESS) == bmGPIF_READ_IN_PROGRESS){
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INPKTEND = USB_TMC_EP_IN;
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INPKTEND = USB_TMC_EP_IN;
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}
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}
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|
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//EA = 0; /* disable all interrupts */
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while(!(GPIFTRIG & bmGPIF_IDLE));
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while(!(GPIFTRIG & bmGPIF_IDLE));
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//EA = 1; /* global interrupt enable */
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|
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/* check if there is data available for an OUT transfer */
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/* check if there is data available for an OUT transfer */
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if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
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//if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
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//if(!(EP2468STAT & bmEP2EMPTY)) {
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//if(!(EP2468STAT & bmEP2EMPTY)) {
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flGPIF &= ~bmGPIF_PENDING_DATA;
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//flGPIF &= ~bmGPIF_PENDING_DATA;
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|
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gpif_trigger_write();
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//EA = 0; /* disable all interrupts */
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flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
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//flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
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}
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//gpif_trigger_write();
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else {
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//EA = 1; /* global interrupt enable */
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gpif_trigger_read();
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//}
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/*else*/ {
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EA = 0; /* disable all interrupts */
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flGPIF |= bmGPIF_READ_IN_PROGRESS;
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flGPIF |= bmGPIF_READ_IN_PROGRESS;
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gpif_trigger_read();
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EA = 1; /* global interrupt enable */
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}
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}
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|
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clear_fifo_gpif_irq();
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clear_fifo_gpif_irq();
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|
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ISR_DEBUG_PORT &= ~bmGPIF_DONE;
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ISR_DEBUG_PORT &= ~bmGPIF_DONE;
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| Line 127... |
Line 133... |
/* check if there is a active IN transfer */
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/* check if there is a active IN transfer */
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if((GPIFREADYSTAT & bmWRX) == bmWRX) {
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if((GPIFREADYSTAT & bmWRX) == bmWRX) {
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flGPIF |= bmGPIF_PENDING_DATA;
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flGPIF |= bmGPIF_PENDING_DATA;
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}
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}
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else {
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else {
|
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//EA = 0; /* disable all interrupts */
|
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if((flGPIF & bmGPIF_READ_IN_PROGRESS) == bmGPIF_READ_IN_PROGRESS) {
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GPIFABORT = 0xFF;
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GPIFABORT = 0xFF;
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SYNCDELAY;
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SYNCDELAY;
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flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
|
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}
|
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//EA = 1; /* global interrupt enable */
|
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//EA = 0; /* disable all interrupts */
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while(!(GPIFTRIG & bmGPIF_IDLE));
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while(!(GPIFTRIG & bmGPIF_IDLE));
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gpif_trigger_write();
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//EA = 1; /* global interrupt enable */
|
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EA = 0; /* disable all interrupts */
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flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
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flGPIF &= ~bmGPIF_READ_IN_PROGRESS;
|
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gpif_trigger_write();
|
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EA = 1; /* global interrupt enable */
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}
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}
|
|
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clear_fifo_gpif_irq();
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clear_fifo_gpif_irq();
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|
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ISR_DEBUG_PORT &= ~bmFIFO_PF;
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ISR_DEBUG_PORT &= ~bmFIFO_PF;
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| Line 225... |
Line 240... |
|
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EA = 1; /* global interrupt enable */
|
EA = 1; /* global interrupt enable */
|
|
|
|
|
/* start gpif read, default state of the gpif to wait for fpga data */
|
/* start gpif read, default state of the gpif to wait for fpga data */
|
|
flGPIF |= bmGPIF_READ_IN_PROGRESS;
|
gpif_trigger_read();
|
gpif_trigger_read();
|
|
|
}
|
}
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