| Line 168... |
Line 168... |
|
|
/* check if this is the first attempt to analyse the bit file header*/
|
/* check if this is the first attempt to analyse the bit file header*/
|
if(usb_tmc_transfer.new_transfer == NEWTRANSFER) {
|
if(usb_tmc_transfer.new_transfer == NEWTRANSFER) {
|
continue_analyse = 0;
|
continue_analyse = 0;
|
fpga_file_header.type = FPGA_TYPE;
|
fpga_file_header.type = FPGA_TYPE;
|
|
usb_tmc_transfer.transfer_size += USB_TMC_HEADER_SIZE;
|
}
|
}
|
|
|
/* first value to read from the header file is the fpga type */
|
/* first value to read from the header file is the fpga type */
|
if(fpga_file_header.type == FPGA_TYPE){
|
if(fpga_file_header.type == FPGA_TYPE){
|
|
|
if(fpga_scan_file(buffer, offset, byte_count, &fpga_file_header) \
|
if(fpga_scan_file(buffer, offset, byte_count, &fpga_file_header) \
|
== FPGA_INFO_COMPLETE) {
|
== FPGA_INFO_COMPLETE) {
|
|
|
/* compare fpga type from header with value in eeprom */
|
/* compare fpga type from header with value in eeprom */
|
if(!eeprom_read(FPGA_TYPE_OFFSET, fpga_type, FPGA_TYPE_LEN)){
|
if(!eeprom_read(FPGA_TYPE_OFFSET, fpga_type, FPGA_TYPE_LEN)){
|
return 0;
|
return 0;
|
}
|
}
|
|
|
| Line 196... |
Line 197... |
}
|
}
|
}
|
}
|
|
|
/* second value to read from the header file is the file length */
|
/* second value to read from the header file is the file length */
|
if(fpga_file_header.type == FILE_LENGTH){
|
if(fpga_file_header.type == FILE_LENGTH){
|
|
|
if(fpga_scan_file(buffer, offset, byte_count, &fpga_file_header) \
|
if(fpga_scan_file(buffer, offset, byte_count, &fpga_file_header) \
|
== FPGA_INFO_COMPLETE) {
|
== FPGA_INFO_COMPLETE) {
|
|
|
((uint8_t*)&file_size)[0] = fpga_file_header.info[2];
|
((uint8_t*)&file_size)[0] = fpga_file_header.info[2];
|
((uint8_t*)&file_size)[1] = fpga_file_header.info[1];
|
((uint8_t*)&file_size)[1] = fpga_file_header.info[1];
|
((uint8_t*)&file_size)[2] = fpga_file_header.info[0];
|
((uint8_t*)&file_size)[2] = fpga_file_header.info[0];
|
((uint8_t*)&file_size)[3] = 0;
|
((uint8_t*)&file_size)[3] = 0;
|
|
|
| Line 213... |
Line 214... |
}
|
}
|
}
|
}
|
|
|
/* adjust the offset and byte_count variables to point to the
|
/* adjust the offset and byte_count variables to point to the
|
* binary data after the header */
|
* binary data after the header */
|
usb_tmc_transfer.transfer_size += USB_TMC_HEADER_SIZE;
|
|
usb_tmc_transfer.transfer_size -= *offset;
|
usb_tmc_transfer.transfer_size -= *offset;
|
|
|
return continue_analyse;
|
return continue_analyse;
|
}
|
}
|
|
|
| Line 239... |
Line 239... |
}
|
}
|
|
|
/* do we still analyze the file header? */
|
/* do we still analyze the file header? */
|
if(file_size == 0) {
|
if(file_size == 0) {
|
if(!app_check_fpga_type_from_header(offset, byte_count)) {
|
if(!app_check_fpga_type_from_header(offset, byte_count)) {
|
|
//print_err("bad\n");
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* are we now finished analyzing? */
|
/* are we now finished analyzing? */
|
if(file_size != 0) {
|
if(file_size != 0) {
|
| Line 264... |
Line 265... |
|
|
//printf_tiny("buffer[0], %d\n",buffer[0]);
|
//printf_tiny("buffer[0], %d\n",buffer[0]);
|
|
|
/* transfer finished, finishing configuration */
|
/* transfer finished, finishing configuration */
|
if(file_size == 0) {
|
if(file_size == 0) {
|
|
//print_info("end\n");
|
if(!fpga_load_end()) {
|
if(!fpga_load_end()) {
|
return 0;
|
return 0;
|
}
|
}
|
usb_tmc_state = TMC_STATE_IDLE;
|
usb_tmc_state = TMC_STATE_IDLE;
|
}
|
}
|
| Line 415... |
Line 417... |
return 0;
|
return 0;
|
}
|
}
|
}
|
}
|
|
|
/* to "delete" means to set the file_size at the beginning of the confguration
|
/* to "delete" means to set the file_size at the beginning of the confguration
|
file slot to zero */
|
* file slot to zero */
|
local_uint32_var = 0;
|
local_uint32_var = 0;
|
spiflash_write(&flash_dr, &flash_adress, (uint8_t*)&local_uint32_var,4);
|
spiflash_write(&flash_dr, &flash_adress, (uint8_t*)&local_uint32_var,4);
|
usb_tmc_state = TMC_STATE_IDLE;
|
usb_tmc_state = TMC_STATE_IDLE;
|
|
|
return 1;
|
return 1;
|
| Line 589... |
Line 591... |
if (!(EP2468STAT & bmEP2EMPTY) && flLOCAL == GECKO3COM_LOCAL){
|
if (!(EP2468STAT & bmEP2EMPTY) && flLOCAL == GECKO3COM_LOCAL){
|
offset = 0;
|
offset = 0;
|
|
|
if(usb_tmc_state == TMC_STATE_IDLE || usb_tmc_transfer.transfer_size == 0){
|
if(usb_tmc_state == TMC_STATE_IDLE || usb_tmc_transfer.transfer_size == 0){
|
|
|
/* start to analyze the data in Endpoint 2 if it is a correct TMC header */
|
/* start to analyze the data in Endpoint 2 if it is a correct TMC
|
|
* header */
|
tmc_header = (tHeader*)EP2FIFOBUF;
|
tmc_header = (tHeader*)EP2FIFOBUF;
|
|
|
/* bTag sanity check. store bTag for correct IN transfer response */
|
/* bTag sanity check. store bTag for correct IN transfer response */
|
if (tmc_header->bTag == ~tmc_header->bTagInverse) {
|
if (tmc_header->bTag == ~tmc_header->bTagInverse) {
|
usb_tmc_transfer.bTag = tmc_header->bTag;
|
usb_tmc_transfer.bTag = tmc_header->bTag;
|
| Line 773... |
Line 776... |
|
|
usb_tmc_state = TMC_STATE_IDLE;
|
usb_tmc_state = TMC_STATE_IDLE;
|
}
|
}
|
}
|
}
|
|
|
usb_tmc_transfer.nbytes_rxd += ((EP2BCH << 8) + EP2BCL - USB_TMC_HEADER_SIZE);
|
usb_tmc_transfer.nbytes_rxd += ((EP2BCH << 8) + EP2BCL - \
|
|
USB_TMC_HEADER_SIZE);
|
|
|
/* finished handling usb package.
|
/* finished handling usb package.
|
* rearm OUT endpoint to receive new data */
|
* rearm OUT endpoint to receive new data */
|
OUTPKTEND = bmSKIP | USB_TMC_EP_OUT;
|
OUTPKTEND = bmSKIP | USB_TMC_EP_OUT;
|
|
|
| Line 912... |
Line 916... |
|
|
// if (--watchdog_count == 0){
|
// if (--watchdog_count == 0){
|
// clear_timer_irq();
|
// clear_timer_irq();
|
// #ifdef DEBUG_LEVEL_ERROR
|
// #ifdef DEBUG_LEVEL_ERROR
|
// print_err("Watchdog timed out! System reset\n");
|
// print_err("Watchdog timed out! System reset\n");
|
//mdelay(100); /* wait 100 ms to give the uart some time to transmit */
|
//mdelay(100); /* wait 100 ms to give the uart some time to
|
|
// * transmit */
|
// #endif
|
// #endif
|
|
|
/* simulate CPU reset */ /* FIXME this stuff here does not work. no idea how to simulate an CPU reset instead... */
|
/* simulate CPU reset */ /* FIXME this stuff here does not work.
|
|
* no idea how to simulate an CPU reset
|
|
* instead... */
|
/* _asm
|
/* _asm
|
ljmp __reset_vector
|
ljmp __reset_vector
|
_endasm;*/
|
_endasm;*/
|
//}
|
//}
|
|
|
| Line 956... |
Line 963... |
/* disconnect USB, so the host doesn't wait for us during the fpga
|
/* disconnect USB, so the host doesn't wait for us during the fpga
|
*configuration process (takes up to 20s) */
|
*configuration process (takes up to 20s) */
|
USBCS |= bmDISCON;
|
USBCS |= bmDISCON;
|
|
|
#ifdef DEBUG_LEVEL_ERROR
|
#ifdef DEBUG_LEVEL_ERROR
|
//ser_init();
|
ser_init();
|
//printf_tiny("hi\n");
|
//printf_tiny("hi\n");
|
#endif
|
#endif
|
|
|
/* set the context switch flag to local operation, not fpga */
|
/* set the context switch flag to local operation, not fpga */
|
flLOCAL = GECKO3COM_LOCAL;
|
flLOCAL = GECKO3COM_LOCAL;
|
| Line 998... |
Line 1005... |
((idata uint8_t*)&file_size)[2] = response_queue.buf[2];
|
((idata uint8_t*)&file_size)[2] = response_queue.buf[2];
|
((idata uint8_t*)&file_size)[3] = response_queue.buf[3];
|
((idata uint8_t*)&file_size)[3] = response_queue.buf[3];
|
spi_base_adress += 4;
|
spi_base_adress += 4;
|
|
|
/* debug stuff */
|
/* debug stuff */
|
response_queue.buf[0] = init_spiflash(&flash_dr);
|
//response_queue.buf[0] = init_spiflash(&flash_dr);
|
IEEE488_set_mav();
|
//IEEE488_set_mav();
|
response_queue.length = 1;
|
//response_queue.length = 1;
|
|
|
/* there is nothing to configure when the filesize is 0 or 0xFFFFFFFF */
|
/* there is nothing to configure when the filesize is 0 or 0xFFFFFFFF */
|
if(file_size == 0 || file_size == 0xFFFFFFFF) {
|
if(file_size == 0 || file_size == 0xFFFFFFFF) {
|
/* show that we don't load a config */
|
/* show that we don't load a config */
|
set_led_ext(ORANGE);
|
set_led_ext(ORANGE);
|
