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https://opencores.org/ocsvn/gecko3/gecko3/trunk
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| Rev 13 |
Rev 35 |
| Line 73... |
Line 73... |
//print_error("en\n");
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//print_error("en\n");
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return;
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return;
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}
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}
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else {
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else {
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bitSPI_CLK = 0; //make shure spi_clk is low before we activate a device
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bitSPI_CLK = 0; //make shure spi_clk is low before we activate a device
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SPI_OE |= bmSPI_MASK; //activate spi bus
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SPI_OE |= bmSPI_OE_MASK; //activate spi bus
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enables &= bmSPI_CS_MASK;
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enables &= bmSPI_CS_MASK;
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SPI_CS_PORT |= bmSPI_CS_MASK; //disable all chipselect signals
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SPI_CS_PORT |= bmSPI_CS_MASK; //disable all chipselect signals
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SPI_CS_PORT &= ~enables;
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SPI_CS_PORT &= ~enables;
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//SPI_CS_OE |= enables;
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SPI_CS_OE |= enables;
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SPI_CS_OE |= bmSPI_CS_MASK;
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SPI_CS_OE |= bmSPI_CS_MASK;
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}
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}
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}
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}
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// setup_enables (0); SPI_CS_PORT |= bmSPI_CS_MASK; \ \
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/** disables all SPI devices and sets the SPI and SPI CS signals to tri-state */
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/** disables all SPI devices and sets the SPI and SPI CS signals to tri-state */
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#define disable_all() { \
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#define disable_all() { \
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setup_enables (0); \
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setup_enables (0); \
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} /* SPI_OE &= ~bmSPI_MASK; \
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SPI_CS_OE &= ~bmSPI_CS_MASK; \
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SPI_CS_OE &= ~bmSPI_CS_MASK; \
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SPI_OE &= ~bmSPI_OE_MASK; \
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} */
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}
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/** \brief Internal: Writes one byte to the SPI bus
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/** \brief Internal: Writes one byte to the SPI bus
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*
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*
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* \param[in] data to write to the bus
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* \param[in] data to write to the bus
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*/
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*/
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