| Line 123... |
Line 123... |
signal s_nbtag_reg_en : std_logic;
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signal s_nbtag_reg_en : std_logic;
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_rd_en : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_fifo_reset : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_load : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_zero : std_logic;
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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signal s_send_mux_sel : std_logic_vector(2 downto 0);
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signal s_send_finished : std_logic;
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signal s_send_finished : std_logic;
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signal s_receive_newdata_set : std_logic;
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signal s_receive_newdata_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_receive_end_of_message_set : std_logic;
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signal s_send_data_request_set : std_logic;
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signal s_send_data_request_set : std_logic;
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| Line 210... |
Line 209... |
s_send_fifo_rd_en <= '0';
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s_send_fifo_rd_en <= '0';
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s_send_fifo_reset <= '0';
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s_send_fifo_reset <= '0';
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s_send_counter_load <= '0';
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s_send_counter_load <= '0';
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s_send_counter_en <= '0';
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s_send_counter_en <= '0';
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s_send_mux_sel <= (others => '0');
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s_send_mux_sel <= (others => '0');
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s_send_finished <= '0';
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s_receive_newdata_set <= '0';
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s_receive_newdata_set <= '0';
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s_receive_end_of_message_set <= '0';
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s_receive_end_of_message_set <= '0';
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s_send_data_request_set <= '0';
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s_send_data_request_set <= '0';
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s_gpif_eom <= '0';
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s_gpif_eom <= '0';
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s_gpif_rx_rd_en <= '0';
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s_gpif_rx_rd_en <= '0';
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| Line 297... |
Line 297... |
elsif state = st21_load_counter then
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elsif state = st21_load_counter then
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s_send_mux_sel <= "101";
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s_send_mux_sel <= "101";
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end if;
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end if;
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if state = st24_wait_for_send_end and i_gpif_tx = '0' then
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if state = st24_wait_for_send_end and i_gpif_tx = '0' then
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s_send_finished <= '0';
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s_send_finished <= '1';
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end if;
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end if;
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if state = st10_signal_receive_new_data then
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if state = st10_signal_receive_new_data then
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s_receive_newdata_set <= '1';
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s_receive_newdata_set <= '1';
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end if;
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end if;
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