| Line 39... |
Line 39... |
--
|
--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
use ieee.std_logic_unsigned.all;
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|
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library work;
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library work;
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use work.GECKO3COM_defines.all;
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use work.GECKO3COM_defines.all;
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|
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|
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entity GECKO3COM_simple_test is
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entity GECKO3COM_simple_test is
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port (
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port (
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i_nReset : in std_logic;
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i_nReset : in std_logic;
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i_sysclk : in std_logic; -- FPGA System CLK
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i_sysclk : in std_logic; -- FPGA System CLK
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-- Interface signals to the EZ-USB FX2
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-- Interface signals to the EZ-USB FX2
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| Line 54... |
Line 56... |
i_WRU : in std_logic; -- write from GPIF
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i_WRU : in std_logic; -- write from GPIF
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i_RDYU : in std_logic; -- GPIF is ready
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i_RDYU : in std_logic; -- GPIF is ready
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o_WRX : out std_logic; -- To write to GPIF
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o_WRX : out std_logic; -- To write to GPIF
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o_RDYX : out std_logic; -- IP Core is ready
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o_RDYX : out std_logic; -- IP Core is ready
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-- bidirect data bus
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-- bidirect data bus
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)
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b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
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-- simple test "user interface" signals
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-- simple test "user interface" signals
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o_LEDrx : out std_logic; -- controll LED receive data
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o_LEDrx : out std_logic; -- controll LED receive data
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o_LEDtx : out std_logic; -- controll LED send data
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o_LEDtx : out std_logic; -- controll LED send data
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o_LEDrun : out std_logic; -- power LED
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o_LEDrun : out std_logic; -- power LED
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i_mode_switch : in std_logic_vector(2 downto 0));
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i_mode_switch : in std_logic_vector(2 downto 0));
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| Line 72... |
Line 74... |
-- CONSTANTS
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-- CONSTANTS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant BUSWIDTH : integer := 32; -- you can choose here 32 or 16
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constant BUSWIDTH : integer := 32; -- you can choose here 32 or 16
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|
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-- lenght of the message stored in the response message rom:
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-- lenght of the message stored in the response message rom:
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constant c_transfer_size_rom : std_logic_vector(31 downto 0) := x"0000000E";
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signal c_transfer_size_rom : std_logic_vector(31 downto 0) := x"0000000E";
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-- we will transmitt 1 MiB data when the pseude random number generator
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-- we will transmitt 1 MiB data when the pseude random number generator
|
-- is used:
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-- is used:
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constant c_transfer_size_prng : std_logic_vector(31 downto 0) := x"00100000";
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signal c_transfer_size_prng : std_logic_vector(31 downto 0) := x"00100000";
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- COMPONENTS
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-- COMPONENTS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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| Line 141... |
Line 143... |
signal s_send_finished : std_logic;
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signal s_send_finished : std_logic;
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|
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signal s_mode : std_logic_vector(1 downto 0);
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signal s_mode : std_logic_vector(1 downto 0);
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signal s_transfer_size_reg_select : std_logic;
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signal s_transfer_size_reg_select : std_logic;
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signal s_transfer_size_reg_en : std_logic;
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signal s_transfer_size_reg_en : std_logic;
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signal s_have_more_data : std_logic;
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signal s_send_counter_reset : std_logic;
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signal s_send_counter_reset : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_en : std_logic;
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signal s_send_counter_equals_transfer_size : std_logic;
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signal s_send_counter_equals_transfer_size : std_logic;
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signal s_prng_en : std_logic;
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signal s_prng_en : std_logic;
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signal s_prng_feedback : std_logic;
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signal s_prng_feedback : std_logic;
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signal s_receive_data_error : std_logic;
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signal s_receive_data_error : std_logic;
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|
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signal s_receive_data_old : std_logic_vector(31 downto 0);
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signal s_receive_data_old : std_logic_vector(31 downto 0);
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signal s_selected_transfer_size : std_logic_vector(31 downto 0);
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signal s_selected_transfer_size : std_logic_vector(31 downto 0);
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signal s_remaining_transfer_size : std_logic_vector(31 downto 0);
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signal s_remaining_transfer_size : std_logic_vector(31 downto 0);
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signal s_subtract_value : std_logic_vector(31 downto 0);
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signal s_send_counter_value : std_logic_vector(31 downto 0);
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signal s_send_counter_value : std_logic_vector(31 downto 0);
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signal s_prng_data : std_logic_vector(31 downto 0);
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signal s_prng_data : std_logic_vector(31 downto 0);
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signal s_message_rom_data : std_logic_vector(31 downto 0);
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signal s_message_rom_data : std_logic_vector(31 downto 0);
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| Line 172... |
Line 174... |
st8_reset_send_counter);
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st8_reset_send_counter);
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signal state, next_state : t_fsmState;
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signal state, next_state : t_fsmState;
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-- XST specific synthesize attributes
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-- XST specific synthesize attributes
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attribute safe_recovery_state of pr_state : signal is "idle";
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attribute safe_recovery_state of state : signal is "st1_idle";
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attribute safe_implementation of pr_state : signal is "yes";
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attribute safe_implementation of state : signal is "yes";
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begin -- behavour
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begin -- behavour
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| Line 224... |
Line 226... |
-- type : combinational
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-- type : combinational
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-- inputs : i_mode_switch
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-- inputs : i_mode_switch
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-- outputs: s_mode
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-- outputs: s_mode
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mode_switch_decoder: process (i_mode_switch)
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mode_switch_decoder: process (i_mode_switch)
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begin -- process mode_switch_decoder
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begin -- process mode_switch_decoder
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if i_mode_switch = "xx1" then
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if i_mode_switch = "001" then
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s_mode <= "00";
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s_mode <= "00";
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elsif i_mode_switch = "x1x" then
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elsif i_mode_switch = "010" then
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s_mode <= "01";
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s_mode <= "01";
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elsif i_mode_switch = "1xx" then
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elsif i_mode_switch = "100" then
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s_mode <= "10";
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s_mode <= "10";
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else
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else
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s_mode <= "00";
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s_mode <= "00";
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end if;
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end if;
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end process mode_switch_decoder;
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end process mode_switch_decoder;
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| Line 246... |
Line 248... |
-- type : combinational
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-- type : combinational
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-- inputs : s_mode, s_prng_data, s_message_rom_data
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-- inputs : s_mode, s_prng_data, s_message_rom_data
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-- outputs: s_send_fifo_data
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-- outputs: s_send_fifo_data
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send_data_mux: process (s_mode, s_prng_data, s_message_rom_data)
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send_data_mux: process (s_mode, s_prng_data, s_message_rom_data)
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begin -- process send_data_mux
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begin -- process send_data_mux
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case i_send_mux_sel is
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case s_mode is
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when "00" => s_send_fifo_data <= s_message_rom_data;
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when "00" => s_send_fifo_data <= s_message_rom_data;
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when "01" => s_send_fifo_data <= s_prng_data;
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when "01" => s_send_fifo_data <= s_prng_data;
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when others => s_send_fifo_data <= (others => 'x')
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when others => s_send_fifo_data <= (others => 'X');
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end case;
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end case;
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end process send_data_mux;
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end process send_data_mux;
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-- purpose: mulitiplexer to select the send transfer size
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-- purpose: mulitiplexer to select the send transfer size
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| Line 263... |
Line 265... |
send_transfersize_mode_mux: process (s_mode, c_transfer_size_rom, c_transfer_size_prng)
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send_transfersize_mode_mux: process (s_mode, c_transfer_size_rom, c_transfer_size_prng)
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begin -- process send_transfersize_mode_mux
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begin -- process send_transfersize_mode_mux
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case s_mode is
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case s_mode is
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when "00" => s_selected_transfer_size <= c_transfer_size_rom;
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when "00" => s_selected_transfer_size <= c_transfer_size_rom;
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when "01" => s_selected_transfer_size <= c_transfer_size_prng;
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when "01" => s_selected_transfer_size <= c_transfer_size_prng;
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when others => s_selected_transfer_size <= (others => 'x')
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when others => s_selected_transfer_size <= (others => 'X');
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end case;
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end case;
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end process send_transfersize_mode_mux;
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end process send_transfersize_mode_mux;
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-- purpose: stores the initial or remaining transfer size
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-- purpose: stores the initial or remaining transfer size
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| Line 289... |
Line 291... |
end if;
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end if;
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end if;
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end if;
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end process remaining_transfer_size_reg;
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end process remaining_transfer_size_reg;
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-- purpose: mulitiplexer to select the final transfer size for the selected mode
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-- type : combinational
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-- inputs : s_mode, c_transfer_size_rom, c_transfer_size_prng
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-- outputs: s_selected_transfer_size
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send_transfersize_mode_mux: process (s_mode, c_transfer_size_rom, c_transfer_size_prng)
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begin -- process send_transfersize_mode_mux
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case s_mode is
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when "00" => s_selected_transfer_size <= c_transfer_size_rom;
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when "01" => s_selected_transfer_size <= c_transfer_size_prng;
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when others => s_selected_transfer_size <= (others => 'x')
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end case;
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end process send_transfersize_mode_mux;
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-- maximum alowed transfer size comparator
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-- maximum alowed transfer size comparator
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s_have_more_data <=
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s_send_have_more_data <=
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'1' when s_remaining_transfer_size > s_receive_transfersize else
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'1' when s_remaining_transfer_size > s_receive_transfersize else
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'0';
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'0';
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|
|
|
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-- purpose: mulitiplexer to select the send transfer size
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-- purpose: mulitiplexer to select the send transfer size
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-- type : combinational
|
-- type : combinational
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-- inputs : s_have_more_data, s_remaining_transfer_size,
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-- inputs : s_have_more_data, s_remaining_transfer_size,
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-- s_receive_transfersize
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-- s_receive_transfersize
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-- outputs: s_send_transfersize
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-- outputs: s_send_transfersize
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send_transfersize_mux: process (s_have_more_data, s_current_transfer_size,
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send_transfersize_mux: process (s_send_have_more_data, s_receive_transfersize,
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s_receive_transfersize)
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s_remaining_transfer_size)
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begin -- process send_transfersize_mux
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begin -- process send_transfersize_mux
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case i_send_mux_sel is
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case s_send_have_more_data is
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when '0' => s_send_transfersize <= s_remaining_transfer_size;
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when '0' => s_send_transfersize <= s_remaining_transfer_size;
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when '1' => s_send_transfersize <= s_receive_transfersize
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when '1' => s_send_transfersize <= s_receive_transfersize;
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when others => s_send_transfersize <= (others => 'X');
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end case;
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end case;
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end process send_transfersize_mux;
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end process send_transfersize_mux;
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-- purpose: up counter for the send transfer size
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-- purpose: up counter for the send transfer size
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| Line 334... |
Line 324... |
send_counter : process (i_sysclk, i_nReset)
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send_counter : process (i_sysclk, i_nReset)
|
begin -- process send_counter
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begin -- process send_counter
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if i_nReset = '0' then -- asynchronous reset (active low)
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
s_send_counter_value <= (others => '0');
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s_send_counter_value <= (others => '0');
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elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
if i_send_counter_reset = '1' then
|
if s_send_counter_reset = '1' then
|
s_send_counter_value <= (others => '0');
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s_send_counter_value <= (others => '0');
|
end if;
|
end if;
|
if i_send_counter_en = '1' then
|
if s_send_counter_en = '1' then
|
s_send_counter_value <= s_send_counter_value + 1;
|
s_send_counter_value <= s_send_counter_value + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process send_counter;
|
end process send_counter;
|
|
|
| Line 371... |
Line 361... |
-- inputs : i_sysclk, i_nReset, s_receive_fifo_data, s_receive_fifo_rd_en
|
-- inputs : i_sysclk, i_nReset, s_receive_fifo_data, s_receive_fifo_rd_en
|
-- outputs: s_receive_fifo_data_old
|
-- outputs: s_receive_fifo_data_old
|
receive_fifo_data_reg: process (i_sysclk, i_nReset)
|
receive_fifo_data_reg: process (i_sysclk, i_nReset)
|
begin -- process receive_fifo_data_reg
|
begin -- process receive_fifo_data_reg
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
s_receive_fifo_data_old <= (others => '0');
|
s_receive_data_old <= (others => '0');
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
if s_receive_fifo_rd_en = '1' then
|
if s_receive_fifo_rd_en = '1' then
|
s_receive_fifo_data_old <= s_receive_fifo_data;
|
s_receive_data_old <= s_receive_fifo_data;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process receive_fifo_data_reg;
|
end process receive_fifo_data_reg;
|
|
|
|
|
-- receive data comparator
|
-- receive data comparator
|
-- (use together with test data with incrementing values)
|
-- (use together with test data with incrementing values)
|
s_receive_data_error <=
|
s_receive_data_error <=
|
'0' when s_receive_fifo_data_old + 1 = s_receive_fifo_data else
|
'0' when s_receive_data_old + 1 = s_receive_fifo_data else
|
'1';
|
'1';
|
|
|
|
|
-- purpose: linear shift register for the pseude random number
|
-- purpose: linear shift register for the pseude random number
|
-- generator (PRNG)
|
-- generator (PRNG)
|
| Line 398... |
Line 388... |
begin -- process prng_shiftregister
|
begin -- process prng_shiftregister
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
if i_nReset = '0' then -- asynchronous reset (active low)
|
s_prng_data <= "01010101 01010101 01010101 01010101";
|
s_prng_data <= "01010101 01010101 01010101 01010101";
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
|
if s_prng_en = '1' then
|
if s_prng_en = '1' then
|
s_prng_data <= s_prng_data(30 downto 0) & s_prng_feedback;
|
s_prng_data(31 downto 1) <= s_prng_data(30 downto 0);
|
|
s_prng_data(0) <= s_prng_feedback;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process prng_shiftregister;
|
end process prng_shiftregister;
|
|
|
-- purpose: feedback polynom for the pseudo random number generator (PRNG)
|
-- purpose: feedback polynom for the pseudo random number generator (PRNG)
|
| Line 410... |
Line 401... |
-- outputs: s_prng_feedback
|
-- outputs: s_prng_feedback
|
s_prng_feedback <= s_prng_data(15) xor s_prng_data(13) xor s_prng_data(12)
|
s_prng_feedback <= s_prng_data(15) xor s_prng_data(13) xor s_prng_data(12)
|
xor s_prng_data(10);
|
xor s_prng_data(10);
|
|
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- finite state machine (moore)
|
-- finite state machine (moore)
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
-- state reg
|
-- state reg
|
| Line 427... |
Line 419... |
end process fsm_state_reg;
|
end process fsm_state_reg;
|
|
|
|
|
-- comb logic
|
-- comb logic
|
next_state_decode: process(state, s_receive_fifo_empty, s_send_fifo_full,
|
next_state_decode: process(state, s_receive_fifo_empty, s_send_fifo_full,
|
s_send_data_request)
|
s_send_data_request, s_send_have_more_data, s_mode,
|
|
s_send_counter_equals_transfer_size)
|
begin -- process next_state_decode
|
begin -- process next_state_decode
|
|
|
--declare default state for next_state to avoid latches
|
--declare default state for next_state to avoid latches
|
next_state <= state; --default is to stay in current state
|
next_state <= state; --default is to stay in current state
|
|
|
| Line 480... |
Line 473... |
s_send_counter_en <= '1';
|
s_send_counter_en <= '1';
|
if s_mode = "01" then
|
if s_mode = "01" then
|
s_prng_en <= '1';
|
s_prng_en <= '1';
|
end if;
|
end if;
|
|
|
if s_send_counter_equals_transfer_size = '1' and s_have_more_data = '0' then
|
if s_send_counter_equals_transfer_size = '1' and
|
|
s_send_have_more_data = '0'
|
|
then
|
next_state <= st1_idle;
|
next_state <= st1_idle;
|
elsif s_send_counter_equals_transfer_size = '1' and s_have_more_data = '1' then
|
elsif s_send_counter_equals_transfer_size = '1' and
|
|
s_send_have_more_data = '1'
|
|
then
|
next_state <= st7_subtract_transfered_data;
|
next_state <= st7_subtract_transfered_data;
|
elsif s_send_fifo_full = '1' then
|
elsif s_send_fifo_full = '1' then
|
next_state <= st6_send_wait;
|
next_state <= st6_send_wait;
|
end if;
|
end if;
|
|
|
| Line 494... |
Line 491... |
|
|
if s_send_fifo_full = '0' then
|
if s_send_fifo_full = '0' then
|
next_state <= st5_send_data;
|
next_state <= st5_send_data;
|
end if;
|
end if;
|
|
|
when st7_subtract_transfered_data
|
when st7_subtract_transfered_data =>
|
s_transfer_size_reg_select <= '0';
|
s_transfer_size_reg_select <= '0';
|
s_transfer_size_reg_en <= '1';
|
s_transfer_size_reg_en <= '1';
|
|
|
if s_send_data_request = '1' then
|
if s_send_data_request = '1' then
|
st8_reset_send_counter;
|
next_state <= st8_reset_send_counter;
|
end if;
|
end if;
|
|
|
when st8_reset_send_counter =>
|
when st8_reset_send_counter =>
|
s_send_counter_reset <= '1';
|
s_send_counter_reset <= '1';
|
|
|
| Line 521... |
Line 518... |
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- RESPONSE MESSAGE ROM
|
-- RESPONSE MESSAGE ROM
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- This file was generated with hex2rom written by Daniel Wallner
|
-- This file was generated with hex2rom written by Daniel Wallner
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use IEEE.numeric_std.all;
|
|
|
entity response_message_rom is
|
entity response_message_rom is
|
port(
|
port(
|
A : in std_logic_vector(3 downto 0);
|
A : in std_logic_vector(3 downto 0);
|
D : out std_logic_vector(31 downto 0)
|
D : out std_logic_vector(31 downto 0)
|
);
|
);
|
