| Line 255... |
Line 255... |
-- inputs : s_mode, s_prng_data, s_message_rom_data
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-- inputs : s_mode, s_prng_data, s_message_rom_data
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-- outputs: s_send_fifo_data
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-- outputs: s_send_fifo_data
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send_data_mux: process (s_mode, s_prng_data, s_message_rom_data)
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send_data_mux: process (s_mode, s_prng_data, s_message_rom_data)
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begin -- process send_data_mux
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begin -- process send_data_mux
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case s_mode is
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case s_mode is
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when "00" => s_send_fifo_data <= s_message_rom_data;
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-- we have to change here the "16bit word order" else the data is
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when "01" => s_send_fifo_data <= s_prng_data;
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-- transmitted in the wrong order
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when "00" => s_send_fifo_data <= s_message_rom_data(15 downto 0) &
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s_message_rom_data(31 downto 16);
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when "01" => s_send_fifo_data <= s_prng_data(15 downto 0) &
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s_prng_data(31 downto 16);
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when others => s_send_fifo_data <= (others => 'X');
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when others => s_send_fifo_data <= (others => 'X');
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end case;
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end case;
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end process send_data_mux;
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end process send_data_mux;
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| Line 457... |
Line 461... |
elsif s_send_data_request = '1' then
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elsif s_send_data_request = '1' then
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next_state <= st3_load_total_transfer_size;
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next_state <= st3_load_total_transfer_size;
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end if;
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end if;
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when st2_get_data =>
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when st2_get_data =>
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if s_receive_fifo_empty = '0' then
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s_receive_fifo_rd_en <= '1';
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s_receive_fifo_rd_en <= '1';
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end if;
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if s_receive_fifo_empty = '1' then
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if s_receive_fifo_empty = '1' then
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next_state <= st1_idle;
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next_state <= st1_idle;
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end if;
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end if;
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| Line 476... |
Line 482... |
s_send_transfersize_en <= '1';
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s_send_transfersize_en <= '1';
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next_state <= st5_send_data;
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next_state <= st5_send_data;
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when st5_send_data =>
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when st5_send_data =>
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if s_send_fifo_full = '0' then
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s_send_fifo_wr_en <= '1';
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s_send_fifo_wr_en <= '1';
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s_send_counter_en <= '1';
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s_send_counter_en <= '1';
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if s_mode = "01" then
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if s_mode = "01" then
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s_prng_en <= '1';
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s_prng_en <= '1';
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end if;
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end if;
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end if;
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if s_send_counter_equals_transfer_size = '1' and
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if s_send_counter_equals_transfer_size = '1' and
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s_send_have_more_data = '0'
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s_send_have_more_data = '0'
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then
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then
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next_state <= st1_idle;
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next_state <= st1_idle;
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