URL
https://opencores.org/ocsvn/gecko3/gecko3/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 11 |
Rev 12 |
| Line 9... |
Line 9... |
|
|
library XilinxCoreLib;
|
library XilinxCoreLib;
|
|
|
library work;
|
library work;
|
use work.USB_TMC_IP_Defs.all;
|
use work.USB_TMC_IP_Defs.all;
|
|
use work.USB_TMC_cmp.all;
|
|
|
entity USB_TMC_IP_tb is
|
entity USB_TMC_IP_tb is
|
|
|
end USB_TMC_IP_tb;
|
end USB_TMC_IP_tb;
|
|
|
|
|
|
|
architecture simulation of USB_TMC_IP_tb is
|
architecture simulation of USB_TMC_IP_tb is
|
| Line 64... |
Line 64... |
-- signals
|
-- signals
|
|
|
signal sim_clk : std_logic;
|
signal sim_clk : std_logic;
|
signal sim_rst : std_logic;
|
signal sim_rst : std_logic;
|
|
|
signal s_RxD, s_TxD, s_LEDrun, s_LEDrxtx : std_logic;
|
signal s_LEDrun, s_LEDtx, s_LEDrx : std_logic;
|
signal s_Switches : std_logic_vector(NUMBER_OF_SW-1 downto 0);
|
signal s_Switches : std_logic_vector(NUMBER_OF_SW-1 downto 0);
|
|
|
|
|
signal sim_1 : boolean := false;
|
signal sim_1 : boolean := false;
|
|
|
| Line 261... |
Line 261... |
--end process writeData;
|
--end process writeData;
|
|
|
if(WRX = '0') then
|
if(WRX = '0') then
|
assert WRX = '0' report "WRX : Waiting on incoming MSG ...." severity note;
|
assert WRX = '0' report "WRX : Waiting on incoming MSG ...." severity note;
|
wait on WRX until WRX= '1';
|
wait on WRX until WRX= '1';
|
|
wait for 7*CLK_PERIOD;
|
RDYU <= '1';
|
RDYU <= '1';
|
assert WRX = '1' report "CORE send data RQ >>>" severity note;
|
assert WRX = '1' report "CORE send data RQ >>>" severity note;
|
else
|
else
|
|
wait for 7*CLK_PERIOD;
|
RDYU <= '1';
|
RDYU <= '1';
|
assert WRX = '1' report "CORE send data RQ >>>" severity note;
|
assert WRX = '1' report "CORE send data RQ >>>" severity note;
|
end if;
|
end if;
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.