| Line 83... |
Line 83... |
wr_en : IN std_logic;
|
wr_en : IN std_logic;
|
almost_empty : OUT std_logic;
|
almost_empty : OUT std_logic;
|
almost_full : OUT std_logic;
|
almost_full : OUT std_logic;
|
dout : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
|
dout : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
|
empty : OUT std_logic;
|
empty : OUT std_logic;
|
full : OUT std_logic;
|
full : OUT std_logic);
|
PROG_EMPTY_THRESH : IN std_logic;
|
--PROG_EMPTY_THRESH : IN std_logic;
|
PROG_EMPTY_THRESH_ASSERT : IN std_logic;
|
--PROG_EMPTY_THRESH_ASSERT : IN std_logic;
|
PROG_EMPTY_THRESH_NEGATE : IN std_logic);
|
--PROG_EMPTY_THRESH_NEGATE : IN std_logic);
|
end component;
|
end component;
|
attribute box_type of coregenerator_fifo_dualclock : component is "black_box";
|
attribute box_type of coregenerator_fifo_dualclock : component is "black_box";
|
|
|
begin
|
begin
|
|
|
| Line 108... |
Line 108... |
wr_en => i_wr_en,
|
wr_en => i_wr_en,
|
almost_empty => o_almost_empty,
|
almost_empty => o_almost_empty,
|
almost_full => o_almost_full,
|
almost_full => o_almost_full,
|
dout => o_dout,
|
dout => o_dout,
|
empty => o_empty,
|
empty => o_empty,
|
full => o_full,
|
full => o_full
|
PROG_EMPTY_THRESH => '0',
|
--PROG_EMPTY_THRESH => '0',
|
PROG_EMPTY_THRESH_ASSERT => '0',
|
--PROG_EMPTY_THRESH_ASSERT => '0',
|
PROG_EMPTY_THRESH_NEGATE => '0'
|
--PROG_EMPTY_THRESH_NEGATE => '0'
|
);
|
);
|
|
|
end wrapper;
|
end wrapper;
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
