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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [fifo_receive.vhd] - Diff between revs 22 and 24

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----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--
--
--  Author:  Christoph Zimmermann
--  Author:  Christoph Zimmermann
--  Date of creation: 17. December 2009
--  Date of creation: 17. December 2009
--  Description:
--  Description:
--      This is a wrapper for a FIFO that was generated with the Xilinx Coregenerator
--      This is a wrapper for a FIFO that was generated with the Xilinx
--    to hide the vendor specific stuff and match our naming conventions.
--      Coregenerator to hide the vendor specific stuff and match our naming
 
--      conventions.
--
--
--  Target Devices:     Xilinx FPGA's due to use of Coregenerator IP cores
--  Target Devices:     Xilinx FPGA's due to use of Coregenerator IP cores
--  Tool versions:      11.1
--  Tool versions:      11.1
--  Dependencies:
--  Dependencies:
--
--
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library work;
library work;
use work.GECKO3COM_defines.all;
use work.GECKO3COM_defines.all;
 
 
entity receive_fifo is
entity receive_fifo is
  generic (
  generic (
    BUSWIDTH : integer := 16);          -- vector size of the FIFO databusses
    BUSWIDTH : integer := 32);          -- vector size of the FIFO databusses
  port (
  port (
    i_din    : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
    i_din    : in  std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
    i_clk    : in  std_logic;
    i_clk    : in  std_logic;
    i_rd_en  : in  std_logic;
    i_rd_en  : in  std_logic;
    i_rst    : in  std_logic;
    i_rst    : in  std_logic;
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      rd_clk : in  std_logic;
      rd_clk : in  std_logic;
      rd_en  : in  std_logic;
      rd_en  : in  std_logic;
      rst    : in  std_logic;
      rst    : in  std_logic;
      wr_clk : in  std_logic;
      wr_clk : in  std_logic;
      wr_en  : in  std_logic;
      wr_en  : in  std_logic;
      dout   : out std_logic_vector(BUSWIDTH-1 downto 0);
      dout   : out std_logic_vector(31 downto 0);
      empty  : out std_logic;
      empty  : out std_logic;
      full   : out std_logic);
      full   : out std_logic);
  end component;
  end component;
 
 
  -- Synplicity black box declaration
  -- Synplicity black box declaration

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